Three-dimensional memory and manufacturing method thereof

Abstract

The embodiment of the invention discloses a three-dimensional memory and a manufacturing method thereof. The method comprises the following steps that a substrate is provided; a first region comprising a peripheral circuit and a second region comprising insulating layers and gate layers which are alternately stacked are formed on the substrate, and the second region comprises a step region with a step structure and a core storage region with a channel structure; dielectric layers are formed on the first region and the second region which are arranged in parallel; first etching is conducted on the dielectric layer to form a peripheral circuit contact hole which penetrates through the dielectric layer and extends into the substrate and a gate contact hole which penetrates through the dielectric layer and extends into the step structure gate layer; a first mask layer comprising a peripheral circuit contact pattern and a channel contact pattern is formed on the dielectric layer; and second etching is conducted on the substrate and the dielectric layer by using the first mask layer to form a peripheral circuit contact hole with increased depth and a channel contact hole which penetrates through the dielectric layer and extends into the channel structure.

Description

technical field [0001] The present application relates to the technical field of semiconductors, in particular to a three-dimensional memory and a manufacturing method thereof. Background technique [0002] The 3D NAND memory structure includes vertically stacked multi-layer gates. The central area of ​​the stacked layer is the core storage area, and the edge area is the step area. The core storage area is used to form the channel structure. The gate layer in the stacked layer is used as each layer. The gate of the storage unit is drawn out through the contact on the step, so as to realize the stacked 3D NAND memory. [0003] After forming the channel structure of the core storage region and the step structure of the step region, the dielectric layer can be covered, and the dielectric layer is etched to form a gate contact hole that penetrates the dielectric layer and extends into the gate layer of the stepped structure, and penetrates the dielectric layer and Extend to per...

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Problems solved by technology

[0004] However, in actual operation, in the process of etching the dielectric layer to obtain the gate contact hole and the peripheral circuit contact hole, while ensuring that the etching amount of the substrate in the peripheral circuit contact hole is sufficient, the gate layer is thinner. When it is used, it may penetrate the gate layer and even cause wrong connection between different conductive layers, which will affect the performance of the device. If the etching amount of the gate in the gate contact hole is small, there may be damage to the peripheral circuit contact hole. Insufficient etching of the substrate

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