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Information processing device

A technology of an information processing device and a control device, which is applied in the fields of electrical digital data processing, instruments, computing, etc., to achieve the effect of preventing memory conflicts

Pending Publication Date: 2021-11-26
ORMON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As a result, there is a problem that the CPU cannot perform processing at a fixed cycle

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach 1

[0026] Hereinafter, an embodiment of one aspect of the present invention (hereinafter also referred to as "this embodiment") will be described based on the drawings.

[0027] §1 Application example

[0028] First, refer to figure 1 and 2 to describe an example of a scene where the present invention is applied. like figure 1 As shown, the unit 20 of this embodiment is an information processing device that is connected to a programmable logic controller (Programmable Logic Controller, PLC) 10 in the control system 1 and operates in cooperation with the PLC 10 . The direct memory access controller (DirectMemory Access Controller, DMAC) 31 in the unit 20 shares the memory 12 in the PLC 10 with the CPU 11 in the PLC 10 , and both communicate with the memory 12 through the serial bus 14 . That is, the CPU 11 and the DMAC 31 share the memory 12 . In the control system 1, the structure for preventing the memory conflict by CPU11 and DMAC31 is introduced.

[0029] like figure 2 ...

Embodiment approach 2

[0067] Hereinafter, another embodiment of the present invention (hereinafter also referred to as "this embodiment") will be described based on the drawings.

[0068] §2 Structural example

[0069] (Structure of Control System 1A)

[0070] image 3 It is a block diagram showing the configuration of main parts of the control system 1A of the present embodiment. In the example of this drawing, the control system 1 includes PLC10, the unit 20, and the unit 20A. image 3 The internal structure of the PLC10 and the unit 20 are respectively the same as figure 1 The internal structures of the PLC 10 and the unit 20 are the same, so detailed descriptions will not be repeated. The unit 20A is the same device as the unit 20 , and the internal structure of the unit 20A is the same as that of the unit 20 . That is, the control system 1A can also be said to be a system including a plurality of units 20 . In this embodiment, in order to distinguish between the two, a reference number A...

Embodiment approach 3

[0091] Hereinafter, another embodiment of the present invention (hereinafter also referred to as "this embodiment") will be described based on the drawings.

[0092] §2 Structural example

[0093] The configuration of the control system 1A of the present embodiment is the same as that of the second embodiment. However, DMAC 31 and 31A simultaneously transfer large-capacity data in the same control cycle as each other. At this time, the periods during which the units 20 and 20A access the memory 12 are time-divided in units of the minimum payload of large-capacity data. The transmission control units 32 and 32A do not output the common mask signal, but output only the mask signal or the mask signal A. Furthermore, the length of the period T1 and the start timing of the period T2 in the same control cycle are different for each unit 20 . Furthermore, for each of the cell 20 and the cell 20A, the start timing of the period T2 in a certain control cycle C1 and the period T2 in ...

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Abstract

An objective of the present invention is to prevent an occurrence of memory contention without causing a computation unit of a control device to execute an arbitration process for preventing the memory contention. Provided is a unit (20) comprising a DMAC (31) which, on the basis of a signal outputted from a time counter which operates in synchronization with a time counter of a PLC, does not communicate with a memory (12) via a serial bus in a control cycle (C1) of a CPU (11) during at least a period (T1) overlapping a period (Tcpu) in which the CPU (11) communicates with the memory (12), and communicates with the memory (12) via the serial bus during a period (T2) which begins after period (T1).

Description

technical field [0001] The present invention relates to an information processing device that operates in cooperation with a control device that performs control of a control object. Background technique [0002] Conventionally, an industrial control system of an embodiment is known in which various units that operate in cooperation with the controller are used in combination in order to reduce the processing load on the industrial controller. In such a system, the following embodiment can also be used, that is, the controller and the unit share the same memory, and the controller or the unit respectively access the shared memory to read and write data. However, if the controller and the unit can access the shared memory disorderly, a "memory conflict" will occur due to the respective accesses occurring at the same timing, and as a result, there may be delays in reading and writing of data that should be processed first The problem. [0003] Therefore, conventionally, for ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/00G06F13/28G06F13/372G06F13/38
CPCG06F13/372G06F13/1605G06F13/1668G06F13/28G06F13/4282
Inventor 玉井俊规
Owner ORMON CORP
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