Method of forming multi-level coplanar metal/insulator films using dual damscence with sacrificial flowable oxide
An oxide and insulating layer technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of difficult to distinguish small surface geometry, difficult to remove ARC and photoresist materials, etc.
Inactive Publication Date: 2004-04-21
INFINEON TECH AG
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Problems solved by technology
Dimples and bumps on the surface of the irregular insulating layer cause difficulty in removing ARC and photoresist material after via etch
In addition, it was found that irregular dips and bumps on the surface of the insulating layer made it difficult for the photoresist layer to resolve small surface geometries
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[0021] The present invention will be described in detail below with reference to several exemplary embodiments shown in the drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well known process steps have not been described in detail in order not to unnecessarily obscure the present invention.
[0022] The present invention relates to an improved method of forming multilevel coplanar metal / insulator films. According to the present invention, the upper metal layer and the electrical interconnects to the lower device layer are formed virtually simultaneously by dual damascene techniques utilizing sacrificial flowable oxides.
[0023] According to one embodiment of the invention, vias are formed through the insulat...
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An improved method of performing a dual damascene etch through a layer stack disposed above a substrate. The layer stack includes an underlying device layer and an insulating layer disposed above the underlying device layer. The method includes forming a trench in a top surface of the insulating layer such that the trench is positioned over the underlying device layer and separated therefrom by insulating material at a bottom of the trench. The method also includes, depositing flowable oxide over the top surface of the insulating layer and into the trench followed by planarizing the flowable oxide down to about a level of the top surface of the insulating layer. Further, the method includes, etching through the flowable oxide within the trench and through insulating material at the bottom of the trench down to the underlying device layer to form a via.
Description
technical field [0001] The present invention relates to a semiconductor device and, more particularly, to an improved method of forming multi-coplanar metal / insulator films by double damascene burial using sacrificial flowable oxides. Background technique [0002] Semiconductor manufacturers must continually improve the power and performance of semiconductor devices while keeping device size to a minimum. In an effort to maintain a small device size, most manufacturers resort to reducing the components in the device to minimize the device size. In addition, as opposed to only horizontal integration that has been proposed to reduce the device area occupied by each component, manufacturers are also adopting methods of vertically integrating more and more components. Vertical integration can generally be achieved in a device by utilizing several conductive layers and interconnecting these conductive layers, for example, by means of interlayer contacts known in the art as via o...
Claims
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Login to View More IPC IPC(8): H01L21/28H01L21/302H01L21/3065H01L21/3205H01L21/768
CPCH01L21/76808H01L21/768
Inventor 克劳斯·费尔德纳弗林德·格雷沃尔伯恩德·沃尔默雷纳·弗罗里安·施纳贝尔
Owner INFINEON TECH AG