Stacked die assembly including dual-sided inter-die bonding connection
A stacked, die-based technology, applied in the direction of electrical components, semiconductor devices, electrical solid-state devices, etc., can solve the problem of increasing the noise level of logic circuits
Pending Publication Date: 2022-07-29
SANDISK TECH LLC
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However, power signals carry high voltages, and routing power signals near logic circuits that include noise-sensitive devices such as sense amplifiers can increase noise levels in logic circuits
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[0025] The present disclosure is directed to a stacked die assembly including double-sided die-to-die bonding connections and a method of forming the same, various aspects of which are described in detail below. Accordingly, a stacked die assembly including multiple dies accommodates inter-die electrical connections without occupying additional wafer space used by semiconductor devices, while minimizing noise and signal interference and parasitic coupling.
[0026] The drawings are not drawn to scale. Where a single instance of an element is shown, multiple instances of an element may be repeated unless explicitly described or otherwise clearly indicated that there is no repetition of the element. Items such as "first," "second," and "third" are used merely to identify similar elements, and different sequence numbers may be employed throughout the specification and claims of the present disclosure. The term "at least one" element is meant to include all possibilities of a sin...
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A plurality of bonding units are provided, each bonding unit of the plurality of bonding units including a respective front die and a back die. The two dies in each bonding cell may be a memory die and a logic die configured to control operation of memory elements in the memory die. Alternatively, the two dies may be memory dies. The plurality of bond units may be attached such that the front outer bond pad has an upwardly facing physically exposed surface and the back outer bond pad of each bond unit has a downwardly facing physically exposed surface. A first set of bond wires may connect a respective pair of front outer bond pads and a second set of bond wires may connect a respective pair of back outer bond pads.
Description
[0001] Related applications [0002] This application claims the benefit of priority of US Non-Provisional Patent Application No. 16 / 886,164, filed on May 28, 2020, and US Non-Provisional Patent Application No. 16 / 886,221, filed on May 28, 2020, the entire contents of these patent applications It is hereby incorporated by reference for all purposes. technical field [0003] The present disclosure relates generally to the field of semiconductor devices, and in particular to stacked die assemblies including double-sided inter-die bond connections and methods of forming the same. Background technique [0004] Multiple semiconductor dies may be stacked together to form a stacked die assembly. A power signal may be transmitted through each of the semiconductor dies in the stacked die assembly. However, power signals carry high voltages, and routing the power signals near logic circuits that include noise-sensitive devices, such as sense amplifiers, can increase noise levels in ...
Claims
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IPC IPC(8): H01L23/00
CPCH01L2224/09181H01L2224/9202H01L2224/04042H01L2224/08145H01L2224/48145H01L25/0657H01L2224/32145H01L2224/32225H01L2224/48227H01L2224/48229H01L2224/48149H01L2224/73215H01L2924/1515H01L24/08H01L24/48H01L24/32H01L24/73H01L24/92H01L2224/9222H01L2224/0401H01L25/50H01L2225/06506H01L2225/0651H01L2225/06568H01L2225/06562H01L23/58H01L2224/05647H01L2224/05124H01L2224/05186H01L2224/05171H01L2224/05644H01L2224/29099H01L2224/05184H01L2224/05664H01L2224/05655H01L2224/45099H01L2224/05166H01L2224/05147H01L2224/05686H01L2224/05684H01L2224/80359H01L2224/05624H01L2224/05657H01L2224/05155H01L2224/73251H01L2224/2919H01L2224/80895H01L2224/80001H01L2224/80896H10B43/40H01L2224/03H01L2224/85H01L2224/83H01L2924/0529H01L2924/052H01L2924/01028H01L2924/0516H01L2924/01074H01L2924/00014H01L2924/013H01L2924/04941H01L2924/0519H01L2924/01027H01L2924/01042H01L2924/0132H01L2924/0496H01L2924/04953H01L2924/05442H01L2924/05042H01L2224/08H01L2224/48H01L2224/32
Inventor H·奇布文戈泽崔志欣R·高塔姆周非R·S·马卡拉R·沙朗帕尼A·拉贾谢哈尔
Owner SANDISK TECH LLC