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Dependence-chain processors

A correlation and descriptor technology, applied in the field of microprocessing, can solve problems such as growth, difficult to expand ILP, excessive hardware complexity, etc.

Inactive Publication Date: 2007-01-10
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] Most existing superscalar techniques are difficult to scale further for more ILP
A small increase in ILP may require excessive hardware complexity

Method used

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  • Dependence-chain processors
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Embodiment Construction

[0020] Exemplary embodiments will be described below with reference to specific configurations. Those skilled in the art will recognize that various changes and modifications can be made while remaining within the scope of the appended claims. In addition, well-known elements, devices, components, circuits, process steps, etc. have not been shown in detail so as not to obscure the invention.

[0021] The present invention involves recasting a program into dependency chains. Dependency chains and information related to them are recorded in a storage device. The present invention processes this recorded information in a dependency chain.

[0022] The dependency chain information is formed by dividing dynamic program flow into traces according to a maximum trace size and control flow boundaries. Then, each trace is further divided into completely independent chains of dependencies along data flow boundaries. Those skilled in the art will recognize that frames or any other typ...

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Abstract

An apparatus and method for a processor microarchitecture that quickly and efficiently takes large steps through program segments without fetching all intervening instructions. The microarchitecture processes descriptors of trace sequences in program order so as to locate and dispatch descriptors of dependence chains that are used to fetch and execute the instructions of the dependence chain in data flow order.

Description

technical field [0001] The present invention relates to the field of microprocessors, and more particularly, the present invention relates to apparatus and methods for executing microprocessor instructions grouped in dependency chains. Background technique [0002] Most current processors belong to the class of processors known as superscalar processors. This category can also be divided into RISC (Reduced Instruction Set Computer) or CISC (Complex Instruction Set Computer) processors. These processors include a number of internal processing units with circuitry to dispatch instructions to the processing units. A superscalar processor fetches a series of instructions in program order. In this architecture, each instruction is a single operation. The dispatch circuitry of a superscalar processor allows multiple instructions to be executed in a single processor cycle using an instruction queue, also known as a pipeline. [0003] The architecture also includes circuitry to ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/38G06F9/30
CPCG06F9/3855G06F9/3836G06F9/3838G06F9/3891G06F9/384G06F9/3808G06F9/3856G06F9/38
Inventor 西拉姆·瓦娅佩亚姆博胡斯拉夫·里赫利克约翰·P·申
Owner INTEL CORP