Latching effect detecting method for CMOS circuit
A test method and technology of latch-up effect, applied in the field of testing, can solve the problems of complex trigger source pulse waveform and inconvenient actual use, and achieve the effect of reducing design cost and use risk, and simple pulse waveform
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[0032] See Figure 8 As shown, the latch-up effect test method of the CMOS circuit of the present invention can be used to test the trigger voltage / current of the CMOS integrated circuit, the accurate value of the maintenance voltage / current, and the secondary breakdown voltage / current anti-latch-up ability parameters. Connect all the input terminals of the device under test to the ground and leave the output terminal floating, and then proceed as follows:
[0033] Step 1: First, perform a DC voltage sweep test on the terminal to be tested until the terminal to be tested is connected to ground, and the trigger voltage Von of the terminal to be tested is obtained. In specific implementation, the scanning range of the DC voltage can start from 0V, the step size is 0.5V, and the current limit is 50mA. It can be seen from the IV characteristic of the power supply terminal that the current is very small when the voltage is less than a certain value, and the current suddenly increases w...
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