Integrated circuit package system with symmetric packaging

Inactive Publication Date: 2009-01-01
STATS CHIPPAC LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Wide spread use of portable computers, including laptops, notebooks, palmtops, personal digital assistants, and handheld computers, has been severely hampered by limited capabilities for expansion or customization.
Having very limited slots meant memory and memory related expansion has been limited to standard product dimensions.
However, integrated circuit density continues to be limited by the area available for mounting chips in a next level system.
However, such multi-chip modules can be bulky.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.

Method used

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  • Integrated circuit package system with symmetric packaging
  • Integrated circuit package system with symmetric packaging
  • Integrated circuit package system with symmetric packaging

Examples

Experimental program
Comparison scheme
Effect test

first embodiment

[0031]Referring now to FIG. 1, therein is shown a top plan view of an integrated circuit package system 100 without encapsulation in the present invention. The integrated circuit package system 100 preferably includes a substrate 102, package connectors 104, and package leads 106. First die connectors 108 can provide electrical connectivity to a first integrated circuit 110 such as a memory device or other device with cooperative or compatible inputs or outputs and the package leads 106.

[0032]Die connection sites 112 such as bond pads of the first integrated circuit 110 can be electrically connected to the package connectors 104 or other devices in the integrated circuit package system 100. The die connection sites 112 can preferably be formed as two parallel rows, one each adjacent opposite edges of the first integrated circuit 110. The package leads 106 can preferably be formed as two parallel rows, one row adjacent the package connectors 104 and the die connection sites 112 adjac...

second embodiment

[0044]Referring now to FIG. 3, therein is shown a top plan view of an integrated circuit package system 300 without encapsulation in the present invention. The integrated circuit package system 300 preferably includes a substrate 302, package connectors 304, and package leads 306. First die connectors 308 can provide electrical connectivity to a first integrated circuit 310 such as a memory device or other device with cooperative or compatible inputs or outputs and the package leads 306.

[0045]First die connection sites 312 such as bond pads of the first integrated circuit 310 can be electrically connected to the package connectors 304 or other devices in the integrated circuit package system 300. The first die connection sites 312 can be formed in any configuration such as two sets of two parallel rows. The first die connection sites 312 can preferably be formed as four rows, two parallel rows each adjacent opposite edges of the first integrated circuit 310. The package leads 306 ca...

third embodiment

[0056]Referring now to FIG. 5, therein is shown a top plan view of an integrated circuit package system 500 without encapsulation in the present invention. The integrated circuit package system 500 preferably includes a substrate 502, package connectors 504, and package leads 506. First die connectors 508 can provide electrical connectivity to a first integrated circuit 510 such as a memory device or other device with cooperative or compatible inputs or outputs and the package leads 506.

[0057]First die connection sites 512 such as bond pads of the first integrated circuit 510 can be electrically connected to the package connectors 504 or other devices in the integrated circuit package system 500. The first die connection sites 512 can be formed in any configuration such as a row. The first die connection sites 512 can preferably be formed as a row adjacent one edge of the first integrated circuit 510. The package leads 506 can preferably be formed as a row adjacent the package conne...

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PUM

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Abstract

An integrated circuit package system comprising: providing a substrate having a first substrate surface and a second substrate surface; forming a first package connector and a second package connector over substantially opposite locations of the first substrate surface and the second substrate surface; and attaching a first integrated circuit and a second integrated circuit adjacent the first package connector over the first substrate surface and the second package connector over the second substrate surface.

Description

TECHNICAL FIELD[0001]The present invention relates generally to integrated circuit systems, and more particularly to a system for integrated circuit packages.BACKGROUND ART[0002]Products using electronic devices and systems have continued to increase across all aspects of our daily lives. With the ever-increasing numbers and scope, the electronic devices further demand increases in storing information and programs. Some of the electronic devices have developed considerable computing ability even within very small areas and dimensional form factors.[0003]These devices can process significant amounts of data or execute sizable programs. Continued development of new application types or functions requires the ability to accommodate additional data or programs for continued use of the existing electronic devices or device form factors.[0004]Wide spread use of portable computers, including laptops, notebooks, palmtops, personal digital assistants, and handheld computers, has been severel...

Claims

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Application Information

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IPC IPC(8): H01L23/48H01L21/58
CPCH01L23/49805H01L24/06H01L2224/05553H01L2224/49171H01L2924/01033H01L2924/00014H01L2924/01082H01L2924/01027H01L2225/06572H01L2225/06562H01L2225/0651H01L2224/85399H01L2224/49433H01L2224/49431H01L2224/4912H01L2224/48227H01L2224/48091H01L2224/05599H01L24/49H01L25/0657H01L2224/45099H01L2924/00H01L2924/14H01L2924/181H01L24/48H01L2924/15333H01L2924/00012H01L23/48H01L23/12
InventorPARK, SOO-SANHONG, BUMJOONLEE, SANG-HOHA, JONG-WOO
OwnerSTATS CHIPPAC LTD