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Data receivers and methods of implementing data receivers in an integrated circuit

Active Publication Date: 2015-06-25
XILINX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Equalization is necessary because backplane channels have frequency-dependent losses that give inter-symbol interference (ISI), causing the e

Method used

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  • Data receivers and methods of implementing data receivers in an integrated circuit
  • Data receivers and methods of implementing data receivers in an integrated circuit
  • Data receivers and methods of implementing data receivers in an integrated circuit

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DETAILED DESCRIPTION OF THE DRAWINGS

[0019]The various circuits and methods set forth below relate to a data receiver implemented in an integrated circuit. The circuits and methods reduce circuit requirements and improve performance by selectively implementing different equalizers and CDR circuits in a data receiver, such as by a data receiver implemented in an integrated circuit. More particularly, separate CDR circuits are implemented to perform the separate functions of receiving data and adjusting a clock phase offset. For example, an Alexander CDR circuit may be implemented to receive data, while a Mueller-Muller CDR circuit may be implemented in the same circuit to adjust a clock phase offset. Separate equalization circuits are implemented with the different CDR circuits, where the equalization circuits are selected for a particular CDR circuit.

[0020]As will be described in more detail below, the circuit arrangements provide significant benefits and overcome various problems wh...

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Abstract

A data receiver implemented in an integrated circuit is described. The data receiver comprises an input receiving a data signal; a first equalization circuit coupled to receive the data signal, wherein the first equalization circuit is used to receive the data of the data signal; and a second equalization circuit coupled to receive the data signal, wherein the second equalization circuit is used to adjust a clock phase offset.

Description

FIELD OF THE INVENTION[0001]The present invention relates generally to integrated circuit devices, and in particular, to data receivers and methods of implementing a data receiver in an integrated circuit device.BACKGROUND OF THE INVENTION[0002]Integrated circuit devices are an important part of many electronic devices, where the operation of an electronic device as a whole depends upon the operation of the integrated circuit devices. Data transmission is an important element of many integrated circuit devices. The speed and reliability of data transmission impacts the operation of an electronic device. Data can be transmitted as serial data or parallel data. Serializer-Deserializers (Serdes) transceivers, also known as Multi-Giga-bit Transceivers, are widely used to communicate digital data over backplanes at extremely high speeds. Receivers of Serdes transceivers have two key functional blocks, including an Equalization block which is responsible for opening up the eyes of a data ...

Claims

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Application Information

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IPC IPC(8): H04L7/00H04L7/033H04L25/03
CPCH04L7/0025H04L7/0331H04L25/03885H04L7/0062H04L7/0334H04L25/03057
Inventor HSIEH, CHENG-HSIANGCHANG, KUN-YUNGSAVOJ, JAFAR
Owner XILINX INC