Non-planar vertical dual source drift metal-oxide semiconductor (vdsmos)

Abstract

A non-planar lateral drift MOS device eliminates the need for a field plate extension, which reduces gate width. In one example, two sources and two comparatively small gates in a raised structure allow for two channels and a dual current with mirrored flows, each traveling into and downward through a center region of a connecting well that connects the substrate with the drain areas and shallow wells containing the source areas, the current then traveling in opposite directions within the substrate region of the connecting well toward the two drains. The source and drain areas may be separate raised structures or isolated areas of a continuous raised structure.

Description

BACKGROUND OF THE INVENTION[0001]1. Technical Field[0002]The present invention generally relates to non-planar drift-type semiconductor devices. More particularly, the present invention relates to a non-planar vertical dual source lateral drift metal-oxide non-planar semiconductor structure lacking a field plate extension.[0003]2. Background Information[0004]Conventional drift MOS (metal-oxide semiconductor) architecture uses a large gate width to accommodate a field plate extension. As semiconductor devices continue to shrink, non-planar devices come into play and space for such a large gate becomes problematic.[0005]Therefore, a need exists to reduce the gate width in a non-planar drift MOS device.SUMMARY OF THE INVENTION[0006]The shortcomings of the prior art are overcome and additional advantages are provided through the provision, in one aspect, of a method of fabricating a non-planar lateral drift metal-oxide semiconductor. The method includes providing a non-planar semiconduc...

AI Technical Summary

Benefits of technology

The present invention provides a method and device for making a non-planar semiconductor structure with alternating source and drain regions. The method involves creating a connecting well, shallow wells encompassing source and drain regions, and sources and drains in each region. When the structure is active, a current flows through a single channel from each source to each corresponding drain. The technical effect of the invention is to create a more efficient semiconductor structure for better current flow and faster performance.

Problems solved by technology

As semiconductor devices continue to shrink, non-planar devices come into play and space for such a large gate becomes problematic.

Images