Semiconductor devices with extended active regions

Abstract

A method of making a semiconductor device is achieved in and over a semiconductor layer. A trench is formed adjacent to a first active area. The trench is filled with insulating material. A masking feature is formed over a center portion of the trench to expose a first side of the trench between a first side of the masking feature and the first active area. A step of etching into the first side of the trench leaves a first recess in the trench. A first epitaxial region is grown in the first recess to extend the first active area to include the first recess and thereby form an extended first active region.

Description

BACKGROUND[0001]1. Field[0002]This disclosure relates generally to semiconductor processing, and more specifically, to forming semiconductor devices having extended active regions.[0003]2. Related Art[0004]Semiconductor processing technologies typically impose various dimensional constraints related to active spaces and active widths. For example, a representative 90 nm node CMOS technology may allow a minimum active space of 140 nm and a minimum active width of 110 nm. Typically, such dimensional constraints are imposed to allow manufacturing tolerances during semiconductor processing and to ensure adequate device isolation. In particular, imposing such dimensional constraints may result in easier patterning of active regions and the subsequent filling of the gaps created by shallow trenches.[0005]Such dimensional constraints, however, reduce design flexibility. For example, in certain instances wider active regions are desired to increase drive current, but cannot be implemented b...

AI Technical Summary

Benefits of technology

This approach increases design flexibility and enhances transistor drive current by widening active regions without compromising manufacturing tolerances or device isolation, achieving extended active regions that comply with existing semiconductor processing technologies.

Problems solved by technology

Semiconductor processing technologies typically impose various dimensional constraints related to active spaces and active widths.

Such dimensional constraints, however, reduce design flexibility.

For example, in certain instances wider active regions are desired to increase drive current, but cannot be implemented because of the rigid dimensional constraints imposed by conventional design and process methodologies.

As an example, in the SRAM cells wider active regions can only be achieved at the cost of an increase in the cell size.

Images