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MRAM arrangement

A storage unit and storage array technology, applied in static memory, digital memory information, information storage, etc., can solve the problem of not being able to use MRAMs

Inactive Publication Date: 2008-01-30
INFINEON TECH AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, this solution cannot be used for MRAMs, so this problem area has not been resolved so far

Method used

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Embodiment Construction

[0027] Figures 5-9 have already been explained in the Introduction.

[0028] In the figures, the same reference numerals are used in each case for mutually corresponding structural parts.

[0029] FIG. 1 shows a chain of MRAM arrays according to an embodiment of the present invention, with selection transistors 5 and MTJ layer sequences 4 parallel to each other. In other words, located above the drain-source path of the select transistor 5 is a sequence of MTJ layers 4 , which are connected in series with each other in a chain and adapted for use in the drain-source path of the select transistor 5 .

[0030] FIG. 2 shows an embodiment of an MRAM arrangement according to the present invention. Here, a plurality of chains with MTJ layer sequences 4 and selection transistors 5 shown in FIG. 1 are arranged parallel to one another, and an individual transistor 7 is also additionally connected to each chain. FIG. 2 also shows the first select line SL1 and the column select line RS...

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Abstract

The invention relates to an MRAM arrangement in which the selection transistors (5) and the MTJ layer sequences (4) lie parallel to each other in a cell. A considerable space saving can thus be achieved.

Description

technical field [0001] The present invention relates to a MRAM (MRAM=magnetoresistive RAM, magnetoresistance) arrangement, including a plurality of memory cells arranged in a memory array and each cell includes at least one MTJ (MTJ=Magnetic Tunnel Junction, magnetic channel junction) layer sequence and A selection transistor, the MTJ layer sequence of each cell is located between the word line and the bit line, which are separated by a distance from each other, the gate of the selection transistor is connected to the first selection line to read data from the memory cell, and the MTJ layer sequence Connect to the second selection line. Background technique [0002] In its simple embodiment, MRAM arrangements - hereinafter referred to simply as MRAMs - comprise memory cells arranged in a memory array and each cell has only a sequence of MTJ layers. Such an MTJ layer sequence is shown in FIG. 5 : a channel barrier layer 1 is located between a soft magnetic layer 2 and a hard...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/16G11C11/15H10B20/00
CPCG11C11/16H01L27/228H10B61/22G11C11/15
Inventor M·弗雷塔格T·罗赫
Owner INFINEON TECH AG
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