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Memory system

A memory and memory bank technology, applied in the field of memory systems, can solve the problems of reduced memory access speed and increased circuit area, and achieve the effect of reducing circuit scale and reducing memory access speed.

Inactive Publication Date: 2008-01-30
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] However, the redundancy repairing device of FIG. 5 has a problem in that the speed of memory access is lowered because, for example, when the defect is repaired by adopting a fusing method that does not slow down the memory access speed, it performs each defect by address translation. repair
[0009] The problem of memory access speed reduction is also due to the fact that each memory access is performed after determining whether the access address coincides with the address of any defective part held by the address generating means
[0010] There is also a problem in that it is necessary to keep the same number of defective addresses and the same number of redundant addresses as the defective part, and the circuit area of ​​the redundant address generating means for holding defective addresses increases as the number of defective addresses increases

Method used

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Embodiment Construction

[0035] Embodiments of the present invention will be described below with reference to the drawings.

[0036] FIG. 1 is a block diagram showing the structure of a memory system 10 according to an embodiment of the present invention. The memory system 10 in FIG. 1 includes a memory 101 , an address conversion circuit 107 , a bank conversion circuit 109 , a defect address register 111 , a hit signal generation circuit 112 and a selector 114 . The memory system 10 receives an input address 106 given when making an access, reads data from the memory 101, and outputs the read data.

[0037] The memory 101 has memory groups 150A, 150B, 151A, 151B, 152A, 152B, 153A, and 153B. To specify vertical positions, group numbers 0, 1, 2, and 3 are used, while either group of columns 1 and 0 is used to designate horizontal positions. Select one of the memory banks by specifying any bank number and any bank column.

[0038] Memory groups 150A, 150B, 151A, 151B, 152A, 152B, 153A, and 153B have...

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PUM

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Abstract

A memory system includes a memory having memory banks each having a redundant region for repairing a defect. When a plurality of defects occur in one of the memory banks, at least one of the defects is repaired by using the redundant region of the memory bank with the defects and at least one other of the defects is repaired by using the redundant region of another of the memory banks.

Description

[0001] Cross References to Related Applications [0002] The entire technology of Japanese Patent Application No. JP2006-203856 filed on July 26, 2006 is hereby incorporated by reference, including claims, specification and drawings. technical field [0003] The invention relates to a memory system for repairing defects in memory. Background technique [0004] A semiconductor memory has been manufactured for screen testing, and when it is determined by the test that the memory has a defective area and the defective area is repaired, a method is employed in accessing the memory which determines whether an input address indicates a defective area in the memory, and when the input When the address in indicates a defective area, the input address is transformed to indicate a redundant area in the memory. In order to enable efficient redundancy repair in memory, a redundancy repair device for memory is disclosed, for example, in Japanese Patent Application Publication No. 2005-1...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/24G11C29/44
CPCG11C29/808
Inventor 大八木睦西川亮太
Owner PANASONIC CORP