Hybrid FIFO data storage method and device for high-performance processor
A data storage device and high-performance processor technology, which is applied in the input/output process of data processing, data conversion, electrical digital data processing, etc., can solve problems such as inability to meet performance requirements, and achieve the effect of fast access speed
Inactive Publication Date: 2020-07-14
NAT UNIV OF DEFENSE TECH
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Problems solved by technology
At this time, the existing RAM-type FIFO and register-type FIFO cannot meet the performance requirements
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[0026] Such as figure 1 As shown, the hybrid FIFO data storage device for high-performance processors in this embodiment includes a RAM memory, a selector, a register bank and a FIFO controller, and the FIFO write data port of the hybrid FIFO data storage device is connected to the input terminal of the RAM memory respectively. , one input end of the selector is connected, the output end of the RAM memory is connected with the other input end of the selector, the output end of the selector is connected with the FIFO read data port of the hybrid FIFO data storage device through the register group, and the RAM memory, selection The control terminals of the device and the register bank are respectively connected with the FIFO controller.
[0027] see figure 1 , the hybrid FIFO in this embodiment is composed of a RAM memory, a register bank and a FIFO controller. RAM memory and register bank are used to store data. The RAM memory receives the FIFO write data from the outside, a...
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The invention discloses a hybrid FIFO data storage method and device for a high-performance processor. The device comprises an RAM memory, a selector, a register set and an FIFO controller. An FIFO write data port is connected with the input end of the RAM and one input end of the selector; the output end of the RAM is connected with the other input end of the selector, the output end of the selector is connected with the FIFO data reading port through the register set, and the control end of the RAM, the control end of the selector and the control end of the register set are connected with the FIFO controller. According to the method, the advantages of the RAM type FIFO and the register type FIFO can be integrated, the characteristics of the high access speed and the large storage capacity are integrated, background data migration can be carried out by utilizing a channel between the RAM and the register set, and RAM access delay is hidden, so that the method has the characteristic ofthe high access speed.
Description
technical field [0001] The invention relates to the field of integrated circuit chip design, in particular to a high-performance processor-oriented, hybrid FIFO data storage method and device at the architecture level and circuit level, high speed, large capacity, and low area overhead. Background technique [0002] FIFO (First In and First Out) data queue is a circuit structure widely used in integrated circuit chips, which is used to cache data, clock domain isolation and control the order of data access. FIFO can be divided into RAM type and register type according to the storage unit. Because the number of transistors required to construct a RAM storage unit is small, but the delay in accessing the RAM storage unit is high, the RAM-type FIFO is suitable for use scenarios with large capacity requirements but low access speed requirements; because the access delay of registers is low, But at the same time, the number of transistors required to build registers is large, so...
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IPC IPC(8): G06F5/06G06F3/06
CPCG06F5/06G06F3/0611G06F3/0629G06F3/0647
Inventor 周宏伟张见曾坤杨乾明张剑锋冯权友张英王勇励楠邓让钰乔寓然龚锐石伟刘威王永文王蕾
Owner NAT UNIV OF DEFENSE TECH