Low power content addressable memory architecture

Abstract

The invention relates to a low power CAM architecture which can address memories. The low power CAM architecture is disclosed. Matchlines of the CAM array are segmented into a pre search portion and a main search portion. After issuing a search command, a pre search operation is conducted on the pre search portion of the matchline. If the result of the pre search is a match, then the main search is subsequently conducted on the main search portion of the matchline. If the result of pre search is a mismatch, then the main-search is disabled, and consequently there is no power dissipation on the main search portion of the matchlines. Pre search and main search operations can be pipelined to maintain high throughput with minimum latency. Power consumption is further reduced by using a matchline sense circuit for detecting a current on the pre search and main search portions of the matchline. Matchlines are decoupled from the sense circuit sense node in order to achieve higher sensing speed and improved sense margins, and dummy matchlines are used to generate timed control signals for latching the output of the matchline sense circuits. The matchlines are initially precharged to a miss condition represented by ground potential and are then undergo accelerated precharge to a preset voltage potential level below VDD to overcome tail-out parasitic current and to minimize the voltage swing of the matchlines to conserve power.

Description

[0001] This application is a divisional application of the invention patent application with the application number 02828188.8, the application date is December 5, 2002, and the invention title is "Content Addressable Memory Architecture with Low Power Consumption". technical field [0002] The present invention relates to addressable memory (CAM), and more particularly to a CAM architecture that reduces power consumption. Background technique [0003] In many conventional memory systems, such as random access memory, binary numbers (bits) are stored in memory cells and a processor assigns a linear address associated with a given cell. Access it. Such systems provide fast access to any part of the memory system, but with certain limitations. In order to facilitate the control of the processor, each operation of accessing the memory must state the address of the required memory storage cell as a part of the instruction. Standard memory systems are not well designed for cont...

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Problems solved by technology

Fourth, the sensing must be stable and have a good sensing margin for reliable sensing

This article also stated that, in theory, the selective precharge technique can be expanded to include more than one stage, but the additional overhead, additional clock phase, and additional buffering do not make it possible to provide additional Gains greater than the single-stage selective precharge suggested in the text

This approach does not take into account the possibility of having multiple matchline segments operating sequentially independent of the clock cycle if reasonably fast processing techniques are available to implement the necessary circuit design

In addition, the method discussed by Zukowski et al. still relies on precharging to a logic "H" state, which uses a large amount of current for the reasons mentioned earlier

[0017] Therefore, current CAM devices are not suitable for low-power applications where battery power must be maintained

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