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Digital frequency synthesis and synchronous circuit

A digital frequency synthesis and synchronization circuit technology, applied in the direction of electrical components, automatic power control, etc., can solve the problems of inappropriate circuits and low frequency index requirements, and achieve the effect of simple and reliable circuits, simple frequency synthesis and synchronization

Inactive Publication Date: 2011-04-06
ZTE CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, it is not the best choice to choose these devices in some applications. Sometimes the frequency index requirements are not so high, or cost factors, circuit board area, etc., it is not suitable to choose the above circuit

Method used

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  • Digital frequency synthesis and synchronous circuit
  • Digital frequency synthesis and synchronous circuit
  • Digital frequency synthesis and synchronous circuit

Examples

Experimental program
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Effect test

example 1

[0050] Example 1, the application of the dual-mode frequency division device.

[0051] A single board in the system needs an 8MHz clock signal, which must be synchronized with the 8MHz input reference clock to receive data signals at an 8MHz rate. After the board is powered on, the clock cannot be interrupted, regardless of whether the external reference clock signal is lost. If the previous method is used, a phase-locked loop circuit is needed. Now there is a 66MHz clock signal on the board. Let us analyze the jitter requirements of the board for the 8MHz clock signal: the data width of the 8MHz rate is 125ns, and the clock period of 66MHz It is 15ns, and the 15ns phase jitter 8MHz clock receiving data will not affect data reception, so the circuit of the present invention is adopted, and the 8MHz data receiving clock synchronized with 8MHz is realized by using a little logic on the board. If the external reference 8MHz clock In the case of loss, the circuit still smooths the...

example 2

[0053] Example 2, the application of the three-mode frequency division device.

[0054] A single board in the system needs a 1KHz clock signal for system timing. The system requires a timing resolution of 1ms. Normally, the high-stability 8KHz clock signal provided by the system should be used as a reference. If the system provides a high-stability If the 8KHz clock signal is lost, the timing function of the board cannot be interrupted. If the previous method is used, a phase-locked loop circuit (VCXO) is needed. Now there is a 2.048MHz crystal oscillator signal on the board. Let’s analyze the jitter requirements of the board for the 8KHz clock signal: the system requires a timing resolution of 1ms. The clock period of 2.048MHz is about 0.5us, which can meet the requirements of the system, so we have adopted the circuit of the present invention, and realized the 8KHz timing clock signal synchronous with the 8KHz reference clock signal provided by the system by using a little l...

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PUM

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Abstract

The invention discloses a numerical frequency synthesis and synchronization circuit, comprising a local crystal oscillator, a multi-mode frequency division device connected with the local crystal oscillator and a phase detector connected with the multi-mode frequency division device; wherein, the local crystal oscillator is used for generating a crystal oscillator signal which is output to the multi-mode frequency division device; the phase detector is used for receiving a reference clock signal or the clock signal on which the frequency division is carried out, and an output signal of the multi-mode frequency division device or the output signal on which the frequency division is carried out, the current phase state is obtained by comparing the phases of the two input signals, and the corresponding control signal is output to the multi-mode frequency division device; the multi-mode frequency division device receives the local crystal oscillator signal and selects the corresponding division frequency count according to the control signal output from the phase detector; the output clock signal after the frequency division is carried out on the local crystal oscillator signal is directly output or output by a fixed frequency divider to the phase detector. In the invention, the devices can be selected according to the practical situation, thus being capable of saving cost while achieving the purpose of the application.

Description

technical field [0001] The invention relates to a method for digital signal synchronization and frequency synthesis in the application of digital circuits such as digital communication and instrumentation, in particular to a digital frequency synthesis and synchronization circuit. Background technique [0002] In circuit design, the commonly used frequency synthesis techniques are: [0003] 1) Phase-locked loop technology: It is composed of voltage-controlled oscillator, frequency divider, reference clock, phase monitor, loop filter and other circuits, as shown in Figure 1. [0004] The characteristics of the phase-locked loop technology: use the reference signal input from the outside to control the frequency and phase of the internal oscillation signal of the loop. A circuit consisting primarily of a phase monitor that compares the frequency of a voltage controlled oscillator with an input carrier signal or a signal from a reference frequency generator. After passing thr...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03L7/08H03L7/18
Inventor 邵贵阳
Owner ZTE CORP