Shallow trench isolation structure and method for forming same

A technology of isolation structures and shallow trenches, which is applied in the manufacture of electrical components, transistors, semiconductors/solid-state devices, etc., can solve problems that do not help improve the performance of PMOS devices, and achieve improved electrical stability, improved performance, and reduced thickness Effect

Active Publication Date: 2011-10-05
SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] However, although releasing the stress in the oxide layer 22 reduces the impact on the performance of the NMOS device, it does not help to improve the performance of the PMOS device.

Method used

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  • Shallow trench isolation structure and method for forming same
  • Shallow trench isolation structure and method for forming same
  • Shallow trench isolation structure and method for forming same

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0069] Please refer to Figure 9 , the semiconductor substrate 100 has a first region 102 and a second region 202 , the first region 102 has at least one trench 108 , and the second region 202 has at least one trench 208 .

[0070] In one of the embodiments, the process of forming the trenches 108 and 208 is as follows:

[0071] Please refer to Figure 6 , firstly, a semiconductor substrate 100 is provided, the semiconductor substrate 100 may be one of single crystal silicon, polycrystalline silicon, and amorphous silicon, and the semiconductor substrate 100 may also be one of a silicon germanium compound and a silicon gallium compound Alternatively, the semiconductor substrate 100 may also include an epitaxial layer or a silicon on insulator (Silicon On Insulator, SOI) structure.

[0072] The semiconductor substrate 100 has a first region 102 and a second region 202 . Wherein, the first region 102 is used to form a PMOS, and the second region is used to form an NMOS.

[0...

Embodiment 2

[0109] Please refer to Figure 9 , provide a semiconductor substrate 100, the semiconductor substrate 100 has a first region 102 and a second region 202, at least one trench 108 is provided in the first region 102, and at least one trench is provided in the second region 202 208.

[0110] In one embodiment, the process for forming the trenches 108 and 208 is the same as the process for forming the trenches in the first embodiment, and will not be repeated here.

[0111] Next, please refer to Figure 18 , forming a first stress layer 404 in the first region 102 and the second region 202 , wherein the first stress layer 404 partially fills the trench 108 in the first region.

[0112] In one of the embodiments, the first stress layer 404 is a compressive stress film layer, specifically, it may be a compressive stress silicon oxide layer, and the method for forming the compressive stress silicon oxide layer may be a high-density plasma chemical vapor phase deposition.

[0113]...

Embodiment 3

[0127] Please refer to Figure 9 , provide a semiconductor substrate 100, the semiconductor substrate 100 has a first region 102 and a second region 202, at least one trench 108 is provided in the first region 102, and at least one trench is provided in the second region 202 208.

[0128] In one embodiment, the process for forming the trenches 108 and 208 is the same as the process for forming the trenches in the first embodiment, and will not be repeated here.

[0129] Next, please refer to Figure 22 , forming a first stress layer 504 in the first region 102 and the second region 202 , wherein the first stress layer 504 partially fills the trench 108 in the first region.

[0130] In one of the embodiments, the first stress layer 504 is a compressive stress film layer, specifically, it may be a compressive stress silicon oxide layer, and the method for forming the compressive stress silicon oxide layer may be a high-density plasma chemical vapor phase deposition.

[0131]...

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Abstract

The invention relates to a method for forming a shallow trench isolation structure. The method comprises the following steps: a semiconductor substrate is provided, wherein the semiconductor substrateis provided with a first area and a second area which are respectively provided with at least one trench; a first stress layer is respectively formed on the first area and the second area, and the first stress layer at least fills the trench in the first area; the first stress layer of the second area is removed; a second stress layer is respectively formed on the first stress layer of the firstarea and the second area, and the second stress layer at least fills the trench in the second area; the second stress layer and the first stress layer are flatted; and the first stress layer and the second stress layers on the first area and the second area are removed. The invention also provides the shallow trench isolation structure and can simultaneously improve the performance for forming anNMOS and a PMOS.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a shallow trench isolation structure and a forming method thereof. Background technique [0002] The shallow trench isolation structure is formed by forming a trench on a semiconductor substrate and filling the trench with a dielectric material. The Chinese patent application document with publication number CN 1649122A discloses a manufacturing method of shallow trench isolation. Figure 1 to Figure 5 It is a schematic cross-sectional view of the structure corresponding to each step of the manufacturing method of the shallow trench isolation disclosed in the Chinese patent application document. [0003] Such as figure 1 As shown, a semiconductor substrate 12 is provided, a pad oxide layer 12A is formed on the semiconductor substrate 12, and then a silicon nitride layer is formed on the pad oxide layer 12A as the first hard mask layer 14. A second hard mask...

Claims

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Application Information

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Patent Type & AuthorityPatents(China)
IPC IPC(8): H01L21/8238H01L21/762H01L27/092
Inventor王国华吴汉明
OwnerSEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP