Unlock instant, AI-driven research and patent intelligence for your innovation.

Low power consumption excitation generating system

A low-power, seeded technology, applied in measurement devices, instruments, measurement electronics, etc., can solve problems such as reducing power consumption, reducing test node activity, and high power consumption for high-frequency integrated circuits

Inactive Publication Date: 2010-04-07
SHANGHAI UNIVERSITY OF ELECTRIC POWER
View PDF0 Cites 5 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0016] The present invention aims at the problem of high power consumption in existing high-frequency integrated circuit testing, and proposes a low-power consumption excitation generation system, which reduces the activity of test nodes, thereby greatly reducing power consumption, and the pseudo-random seed generator generates the final test The seed of the stimulus makes the low-power stimulus pseudo-random, and the test stimulus has no redundancy. While reducing the test power consumption, the test time is not increased, and the fault coverage rate will not be affected.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Low power consumption excitation generating system
  • Low power consumption excitation generating system
  • Low power consumption excitation generating system

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0024] Low power test stimulus generation systems such as figure 2 As shown, the system includes an n-bit counter 2 (n-bitCounter), a single input jump encoder 3 (Single Input Change Encoder), a pseudo-random seed generator 1Seed Generator (SG), and an XOR logic combination.

[0025] figure 2 Among them, the n-bit counter 2 carries out 0~2 n -1 count, single input jump Encoder 3 encodes the data produced by Counter 2, producing 2 n A single input jump vector, and then different or 5 with the pseudo-random seed 'SEED' generated by the pseudo-random seed generator 1 (SG), the pseudo-random seed generator 1 and the counter 2 are controlled by the same test clock TCK. From the n-bit output of the counter 2, select the low m-bit (mm A single input transition vector reduces the activity of the test node, resulting in a significant reduction in power consumption.

[0026] Pseudo-random seed generator 1 generates the seeds of the final test stimulus, which makes the low-power sti...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to a low power consumption excitation generating system, which comprises an n-bit counter, a single-input hopping encoder, a pseudo-random seed generator and an XOR logic combination, wherein by adding certain 'XOR' and 'NOR' logic circuits to the simple counter, a single-input hopping test excitation without redundancies can be achieved. For n input tested circuits, 2n single-input hopping test vector sets can be generated maximally, all possible test vector combinations are covered, and while the test power consumption is reduced, the testing time is not increased and the fault coverage is not influenced.

Description

technical field [0001] The invention relates to the technical field of integrated circuit testing, in particular to a low power consumption excitation generation system. Background technique [0002] With the development of integrated circuit technology and design technology, the scale of integrated circuits can reach tens of millions of gates, and more and more chip clocks work at GHz, which directly leads to a huge increase in chip power consumption, and at the same time leads to changes in chip testing. It's extraordinarily complicated. In the past, because the test was performed at a frequency much lower than the normal working mode, the problem of power consumption during the test was not very prominent. However, with the advancement of test technology, the chip must be tested at the working frequency in many cases, which makes the power consumption of the test surge. Due to the great correlation between the data during normal operation, but the correlation between th...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/3183G01R31/3187
Inventor 叶波
Owner SHANGHAI UNIVERSITY OF ELECTRIC POWER