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Simulation method of FLASH/electrically erasable programmable read-only memory (EEPROM)

An emulation method and function technology, applied in the field of smart card chip emulation, can solve the problems of difficult assembly and realization, no FLASH/EEPROM realization form, etc.

Inactive Publication Date: 2011-07-27
BEIJING CEC HUADA ELECTRONIC DESIGN CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] 1. Usually, an emulator is required before the chip is implemented, and at this time there is no implementation form of FLASH / EEPROM, especially as an embedded FLASH / EEPROM module
[0004] 2. Considering the compatibility of the emulator, FLASH / EEPROM has various packaging forms and pin arrangements, and it is not easy to assemble on the same PCB.

Method used

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  • Simulation method of FLASH/electrically erasable programmable read-only memory (EEPROM)
  • Simulation method of FLASH/electrically erasable programmable read-only memory (EEPROM)
  • Simulation method of FLASH/electrically erasable programmable read-only memory (EEPROM)

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Embodiment Construction

[0011] The present invention will be further described below in conjunction with the accompanying drawings.

[0012] A kind of NVRAM-based FLASH / EEPROM emulation method disclosed by the present invention utilizes the characteristic that NVRAM can save data after power-off, emulates the data storage function of FLASH / EEPROM; uses logic circuit to emulate the erasure and programming of FLASH / EEPROM Timing; use FPGA internal RAM to simulate the page buffer area of ​​FLASH / EEPROM; use FPGA internal logic to realize the function of erasing "1" and writing "0" of FLASH / EEPROM.

[0013] The logic circuit is described as follows:

[0014] Design a counting logic such as figure 2 As shown, whether it is an erase operation or a programming operation, the address signal of NVRAM is generated by the output signal of the counter and the external input address signal at the same time. According to the timing requirements of FLASH / EEPROM. At the same time, an internal page buffer area is...

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Abstract

The invention provides a simulation method of FLASH / electrically erasable programmable read-only memory (EEPROM), which is based on a logical add non-volatile random access memory (NVRAM) combination and belongs to the technical field of intelligent card simulation. A structure and a time sequence based on the FLASH / EEPROM are realized by adopting a logic mode, a mode of a counter is adopted in the logic to realize the time sequence of the FLASH / EEPROM, and various logic signals are realized on the basis of realizing the time sequence of the FLASH / EEPROM.

Description

technical field [0001] The invention relates to the technical field of smart card chip emulation. Background technique [0002] In the smart card chip emulator, the emulation of the FLASH / EEPROM module will be involved, [0003] 1. Usually, an emulator is required before chip implementation, but at this time there is no implementation form of FLASH / EEPROM, especially as an embedded FLASH / EEPROM module. [0004] 2. Considering the compatibility of the emulator, FLASH / EEPROM has various packaging forms and pin arrangements, and it is not easy to assemble on the same PCB. [0005] A method of simulating FLASH / EEPROM by using NVRAM plus logic circuit proposed by the present invention can solve such problems. Contents of the invention [0006] The present invention adopts the function of NVRAM power-off data not being lost, simulates the data non-volatile characteristics of FLASH / EEPROM; adopts the combination of FPGA logic and NVRAM to realize the simulation of FLASH / EEPROM,...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/36
Inventor 李丹
Owner BEIJING CEC HUADA ELECTRONIC DESIGN CO LTD
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