Microprocessor integrated circuit and correlation debug method
A microprocessor and integrated circuit technology, which is applied to the generation of response errors, error detection of redundant data in hardware, etc., can solve problems such as tracking routines that cannot be executed
Active Publication Date: 2012-07-11
VIA TECH INC
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However, some events of importance for debugging or tuning may occur asynchronously during the execution of instructions, that is, during the execution of instructions, some of which may take many clock cycles to execute, during which the trace routine cannot implement
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[0031] see figure 1, is a block diagram showing a microprocessor integrated circuit 100 according to an embodiment of the present invention. The microprocessor integrated circuit 100 includes a main processor 102 and a service processor (SPROC for short) 134 . The term "primary processor" or "processor" or "microprocessor" herein may be considered to be a portion of microprocessor integrated circuit 100 that is not service processor 134 . In one embodiment, the main processor 102 is an x86 architecture (also referred to as IA-32) processor 102 . However, main processor 102 may also employ other processor architectures. A processor is an x86 architecture processor if it can correctly execute most applications designed for x86 processors. If an application program can obtain the expected execution results, the application program can be said to be executed correctly. Specifically, the main processor 102 can execute instructions of the x86 instruction set and includes a set o...
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The present invention provides a microprocessor integrate circuit, including a first processor and a second processor, an internal memory and a bus interface unit. The internal memory is accessed by the first processor and the second processor, and the bus interface unit is connected with an external bus outside the microprocessor to access an external memory outside the microprocessor. The bus interface unit, the external bus and the external memory may be accessed by the second processor and is not accessed by the first processor. The first processor writes the debug information into the internal memory. The first processor is used to detect an event and provide an event notification corresponding to the event to the second processor. The second processor is coupled to the bus interfaceunit and used to execute a microcode routine according to the event notification received from the first processor. The microcode routine reads the debug information from the internal memory and writes to the external memory through the bus interface unit and the external bus so as to debug the second processor.
Description
technical field [0001] The present invention relates to debugging and performance adjustment of microprocessors, in particular to debugging and performance adjustment of service processors. Background technique [0002] The processor contains a set of microcode routines that are dormant until activated by a software write instruction to the control register (eg, the WRMSR instruction). This group of microcode routines is called “tracer” herein, which can be used as a tool for debugging and tuning the processor. Once started, the trace routine can be triggered by various events, causing it to collect processor status information and write the processor status information to a specified address in memory, so that the processor status information can be monitored by the external processor bus. obtained by the logic analyzer. State information may include scratchpad sets; Translation-Lookaside Buffers (TLBs); caches, such as data caches, branch destination caches, and level-2 ...
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IPC IPC(8): G06F11/18
Inventor G・葛兰・亨利陈巨轩
Owner VIA TECH INC