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Semiconductor device and method for production thereof

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, transistors, etc., can solve problems such as low Ge content, shallow grooves, and compressive strain in hard-to-channel regions

Inactive Publication Date: 2010-12-22
FUJITSU SEMICON LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in order to make the thickness of the SiGe layer below the limit film thickness, it is necessary to make the groove shallow, and it is difficult to generate sufficient compressive strain in the channel region.
[0008] Therefore, in the prior art, in order to ensure normal operation, the Ge content was kept low.

Method used

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  • Semiconductor device and method for production thereof
  • Semiconductor device and method for production thereof
  • Semiconductor device and method for production thereof

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no. 1 approach

[0054] Next, a first embodiment will be specifically described with reference to the drawings. However, for convenience, the structure of the semiconductor device will be described together with the method of manufacturing the semiconductor device. The first embodiment mainly relates to p-channel MOS transistors. Figure 3A ~ Figure 3M It is a sectional view showing the manufacturing method of the semiconductor device of the first embodiment in order of processes.

[0055] First, if Figure 3A As shown, on the surface of a p-type silicon substrate 11, an element isolation insulating film 12 for dividing nMOS region 1 and pMOS region 2 is formed by STI (Shallow Trench Isolation: Shallow Trench Isolation) method. The nMOS region 1 is a region where an n-channel MOS transistor is to be formed, and the pMOS region 2 is a region where a p-channel MOS transistor is to be formed. When the element isolation insulating film 12 is formed, first, a silicon oxide film with a thickness ...

no. 2 approach

[0081] Next, a second embodiment will be specifically described with reference to the drawings. Wherein, for convenience, the structure of the semiconductor device and the manufacturing method of the semiconductor device will be described together. The second embodiment mainly relates to n-channel MOS transistors. In n-channel MOS transistors, it is necessary to generate lateral tensile strain in the channel region. For this purpose, for example, it is only necessary to form a SiC layer in the groove. In addition, by appropriately controlling the C content when forming the SiC layer, the same effect as that of the first embodiment can be obtained also in the n-channel MOS transistor. Figure 9A ~ Figure 9E It is a cross-sectional view showing the manufacturing method of the semiconductor device according to the second embodiment in order of steps.

[0082] First, in the same manner as in the first embodiment, the processes up to the formation of the silicon oxide film 18 an...

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Abstract

A recess (21) is formed in a pMOS region (2). An SiGe layer (22) is formed so as to cover the bottom surface and the side wall of the recess (21). An SiGe layer (23) having a lower Ge content than that in the SiGe layer (22) is formed on the SiGe layer (22). An SiGe layer (24) is formed on the SiGe layer (23).

Description

technical field [0001] The present invention relates to a semiconductor device capable of high-speed operation and its manufacturing method. Background technique [0002] In LSI (large-scale integration: large-scale integration) such as transistors with a process rule of 90nm node or later, the standby leakage current (off-leak current) decreases with the miniaturization of components. cannot be ignored. Therefore, it is difficult to improve the device performance only by simply miniaturizing the gate length of the transistor, and a new attempt to improve the device performance is required. [0003] In such an ultra-miniaturized transistor, the area of ​​a channel region located directly under the gate electrode is very small compared with conventional transistors. It is well known that in such a case, the mobility of carriers (electrons and holes) moving in the channel region is greatly affected by the stress applied to the channel region. Therefore, attempts have been m...

Claims

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Application Information

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IPC IPC(8): H01L21/336H01L29/78
CPCH01L21/823807H01L29/7833H01L21/823814H01L29/165H01L29/6656H01L29/66636H01L29/7848H01L29/6659H01L29/66545H01L29/045H01L29/665
Inventor 田村直义岛宗洋介前川裕隆
Owner FUJITSU SEMICON LTD
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