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Clock generating apparatus having low clock jitter and related method thereof

A technology of a clock generation device and generation method, which is applied in the direction of automatic power control and electrical components, and can solve the problems of voltage mode control signal errors, output clock phase/frequency errors, etc.

Active Publication Date: 2011-01-26
REALTEK SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In particular, the charge pump also often has leakage current
Therefore, during phase detection, an error will be introduced into the current mode signal, resulting in an error in the voltage mode control signal and in the phase / frequency of the output clock.

Method used

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  • Clock generating apparatus having low clock jitter and related method thereof
  • Clock generating apparatus having low clock jitter and related method thereof
  • Clock generating apparatus having low clock jitter and related method thereof

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Embodiment Construction

[0026] Read the following detailed description with reference to the accompanying drawings of the present invention, wherein the accompanying drawings of the present invention introduce various embodiments of the present invention by way of illustration and provide an understanding of how to implement the present invention. The embodiments of the present invention provide sufficient content for those skilled in the art to implement the embodiments disclosed in the present invention, or implement the embodiments derived from the contents disclosed in the present invention. It should be noted that these embodiments are not mutually exclusive, and some embodiments can be properly combined with one or more other embodiments to form new embodiments, that is, the implementation of the present invention is not limited to the following The disclosed embodiments.

[0027] figure 1 is a functional block diagram showing an embodiment of the clock generating device 100 according to the p...

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Abstract

A clock generating apparatus is disclosed, which comprises a first phase detecting circuit configured to receive a first clock and a second clock to output a first detecting output signal; a second phase detecting circuit configured to receive the first clock and the second clock to output a second detecting output signal; a summing circuit to sum the first detecting output signal and the second detecting output signal to generate a control signal; a loop filter to filter the control signal into a refined control signal; and a controlled oscillating circuit to generate the output clock in accordance with a control by the control signal.

Description

[0001] This invention claims foreign priority to U.S. Provisional Application (Application No. 61 / 226,657), filed July 17, 2009, entitled "Phase Locking Device for Reducing Clock Jitter Caused by Leakage Current" and its method (METHOD AND APPARATUS OF PHASE LOCKING FOR REDUCING CLOCK JITTER DUE TO CHARGE LEAKAGE)". And the content of the provisional application is cited by reference in the present invention. technical field [0002] The invention relates to a clock generating device and a related method, in particular to a clock generating device with low clock jitter and a related method. Background technique [0003] The clock generating device is a widely used electronic device, such as a phase locked loop (Phase Lock Loop, PLL). The phase-locked loop receives a reference clock and generates an output clock accordingly, and the output clock is phase-locked with the reference clock. Generally speaking, a typical PLL includes: a control circuit and a controlled oscillato...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03L7/06
CPCH03L7/087H03L7/0891
Inventor 林嘉亮
Owner REALTEK SEMICON CORP
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