Verification system and method for memory controller

Abstract

The invention is suitable for the field of verification, and provides a verification system and a verification method for a memory controller. The system comprises a test case generator, a bus driver, a monitoring unit and a scoreboard, wherein the test case generator is used for generating at least one test case; the bus driver is used for generating a control event according to the test case generated by the test case generator, converting the test case into the interface bus timing of the memory controller and sending the interface bus timing to the memory controller simultaneously; the monitoring unit is used for monitoring a monitoring event which is generated by the memory controller according to the received interface bus timing; and the scoreboard is used for judging whether the memory controller works normally or not according to the control event generated by the bus driver and the monitoring unit monitored by the monitoring unit. By establishing a module level-based verification system for the memory controller, a plurality of channels of the memory controller are parallelly and fully verified, so the system has high reusability and efficiency.

Description

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AI Technical Summary

Benefits of technology

This patented describes an improved method called modular storage device (MS) verifier systems. These are designed specifically for testing MSC's performance or other components on computer networks. They use specialized hardware modules to create tests during production runs without affecting their overall functionality. Additionally, they can verify each channel individually through simulation techniques like simulating network traffic between different devices connected via communication lines. Overall these improvements improve the reliance and security of data transmission over various types of networking infrastructure such as LANs.

Problems solved by technology

This patented describes an integrated circuit design process where different components like graphics/video coding units require accesses outside their own chip area. However, current methods have limitations when trying to perform direct comparative analysis due to the complexity involved in transmitting data over these interfaces. Additionally, some systems allow concurrent execution of certain functions without interference caused by others. Current solutions either involve setting specifications for each component separately or performing simulations beforehand, making them difficult to validate accurately during simulation time.

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