A Design Verification Method for Passive Tag Chip

A design verification and passive tag technology, which is applied in the field of passive tag chip design verification, can solve problems such as imperfection, code coverage and function coverage that are difficult to meet the requirements of filming, difficult positioning, etc., and achieve an improved success rate Effect

Active Publication Date: 2019-02-05
WUXI KEYBRIDGE ELECTRONICS TECH CO LTD
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AI Technical Summary

Problems solved by technology

The code coverage and function coverage of this verification method are difficult to meet the requirements of filming, and may cause imperfect and imperfect implementation of the RFID protocol, which may cause some functions of the produced chips to be missing, and some functions to meet the requirements But the performance does not meet the requirements, and it is difficult to locate where the problem occurs

Method used

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  • A Design Verification Method for Passive Tag Chip

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Embodiment Construction

[0044] figure 1 As shown, a design verification method for a passive tag chip is disclosed, including the following steps:

[0045] Step (1), determine the RFID standard protocol to determine the various functions and performance indicators to be achieved by the RFID; wherein, the above-mentioned RFID standard protocol can be formulated by the state or by the RFID industry.

[0046] In step (2), after the RFID standard protocol is determined, the logic verification engineer begins to write the RTL (RegisterTransferLevel register transfer level circuit) logic verification specification. When writing, it is necessary to refer to the logic detailed design plan written by the logic design engineer in step (12), and the RTL The verification specifications in the logic verification specification must cover all the functions and performance indicators in the standard protocol of step (1); after the logic verification specification is written, it needs to be reviewed by logic and algo...

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Abstract

The invention discloses a design verification method for a passive tag chip. The method comprises the design verification steps of designing an algorithm, verifying the algorithm, designing an RTL (Register Transfer Level) and verifying the RTL. According to the design verification method, a cross-implementation and cross-verification design method is adopted, and thorough implementation and thorough complete verification of an RFID (Radio Frequency Identification) standard protocol can be achieved, so that the success rate of one-time chip delivery is greatly increased.

Description

technical field [0001] The invention relates to a design verification method for a passive tag chip. Background technique [0002] At present, the design and implementation of RFID protocols in the current industry are generally separated from logic and algorithm, or directly implemented by logic, but in fact logic and algorithm should complement each other, that is, they are independent of each other and closely linked. The digital part design verification of the current RFID tag chip is generally implemented by the designer using verilog code, and the verifier instantiates the RTL code into the verification environment as a DUT module under test, stimulates it and checks the output. The code coverage and function coverage of this verification method are difficult to meet the requirements of filming, and may cause imperfect and imperfect implementation of the RFID protocol, which may cause some functions of the produced chips to be missing, and some functions to meet the re...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
CPCG06F30/367
Inventor 蔡友向晓安张建王立泉
Owner WUXI KEYBRIDGE ELECTRONICS TECH CO LTD
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