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68results about How to "Fully verified" patented technology

Geometric positioning precision analysis method for remote sensing satellite without ground control point

A geometric positioning precision analysis method for a remote sensing satellite without a ground control point comprises the following steps: S1, establishing a strict imaging model, and rewriting the strict imaging model to obtain a strict model geometric positioning equation; S2, generating RPC parameters independent of terrains; S3, checking the absolute geometric positioning precision of theRPC coefficient of the image product according to an image angular point method, and judging whether the RPC coefficient of the image product can be used as the reference data of geometric precision analysis and checking or not; verifying the internal coincidence precision of the RPC coefficient generated without depending on a terrain method according to a check point method, and eliminating errors possibly introduced by RPC coefficient calculation; according to a cross validation method, obtaining the relative precision of the RPC coefficient generated without depending on a terrain method and the RPC coefficient of the image data product; and obtaining a direct geometric positioning precision analysis conclusion of the on-orbit optical remote sensing satellite. According to the method,the analysis and calculation of the geometric positioning precision of the remote sensing satellite are realized.
Owner:CHINA ACADEMY OF SPACE TECHNOLOGY

Composite material structure static strength and fatigue strength integrated test verification method

The invention discloses a composite material structure static strength and fatigue strength integrated test verification method. According to the method aiming at material characteristics and structure of a composite material, the requirements that cyclic load needs to be considered in composite material static strength verification, residual bearing capacity needs to be considered after the cyclic load, and residual strength evaluation needs to be carried out after fatigue verification are met, actual experience is combined, the method for verifying the static and fatigue test of the composite material structural component on the same test piece is provided, the technical bottleneck of verification of the composite material structural component is solved, a structural static strength andfatigue strength integrated verification chain of a composite material structural component 'limited load static-fatigue-limit load static-fatigue (damage tolerance)-limited (limit) load static force'is formed, so that the composite material structural component is fully verified, the development period can be shortened, the number of test pieces is reduced, the cost is reduced, and the flight safety level of an aircraft is further improved.
Owner:CHINA HELICOPTER RES & DEV INST

Method and system for verifying timing sequence calibration function of dynamic random access memory (DRAM) controller

ActiveCN102385547AFull verification of the calibration functionThe checksum function is verified for fullFunctional testingStatic random-access memoryRandom access memory
The invention is applied to the technical field of electronics, which provides a method and a system for verifying a timing sequence calibration function of a dynamic random access memory (DRAM) controller. The method comprises steps of performing static delay according to preset static delay value which is random value or traverse value in designated range; generating a test case event describing operations executed by a data transmission bus connected with the DRAM controller; generating a control event according to the test case event; monitoring and obtaining a monitoring event which includes an order part and a data part; and obtaining accurate timing sequence calibration of the DRAM controller when the order part and the data part in the monitoring event are respectively identical with an order part and a data part in the control event. By means of the preset static delay value generated in random or traversal mode in the designated range, the timing sequence calibration function of the DRAM controller is verified, thereby achieving the purpose of verifying the timing sequence calibration function as comprehensive as possible and obtaining complete verification.
Owner:ANYKA (GUANGZHOU) MICROELECTRONICS TECH CO LTD

Assertion-based parameterization verification system of interface time sequence of storage controller

The invention provides an assertion-based parameterization verification system of an interface time sequence of a storage controller and relates to the technical field of verification of integrated circuits. The system comprises a configuration unit, a control unit, an assertion document library, a storage controller to be verified and a detection unit, wherein the configuration unit is used for transmitting configuration parameters to the assertion document library; the control unit is used for transmitting control parameters to the assertion document library; the assertion document library is used for selecting assertion documents needed by verification according to values of the configuration parameters and the control parameters, verifying the needed assertion document, matching an interface signal time sequence with an interface signal time sequence requirement, generating matching information and transmitting the matching information to the detection unit; the storage controller to be verified is used for transmitting the interface signal time sequence to the assertion documents needed by verification and modifying the interface signal time sequence according to failure matching information; the detection unit is used for transmitting the failure matching information to the storage controller to be verified when detecting a matching failure signal. Through the assertion-based parameterization verification system of the interface time sequence of the storage controller, plenty of verification time can be reduced; the working difficulty is reduced; and the accuracy of the verification is improved.
Owner:BEIJING MXTRONICS CORP +1

Industrial personal computer with multi-image shared memory

The invention discloses an industrial personal computer with a multi-image shared memory. The industrial personal computer mainly comprises a display apparatus, a display and control processing module, a display interface module, an input interface module, and a data storage module, wherein the display and control processing module comprises at least two function sub-modules and processes an input signal sent by the input interface module. Each function sub-module generates a corresponding display operation image and the corresponding display operation image is displayed on the display apparatus; and image data of display regions such as background image display regions and the like of different display operation images is stored by adopting the shared memory, so that the storage space for displaying the image data required by the images is greatly saved; the industrial personal computer disclosed by the invention does not contain complex hardware such as a CPU, a display card and the like, and complex software such as an operation system, display operation image software and the like in a running process; a system is simple, low in cost and easy to fully test and verify; and the industrial personal computer has the characteristics of very high function security and information security.
Owner:SHANGHAI LINGXIAN ELECTRONICS SCI & TECH LTD

Register transport level N-modular redundancy verifying method

The invention discloses a register transport level N-modular redundancy semi-automatization verifying method. The method comprises the steps of checking output of registers of a platform to be verified of n-modular redundancy; receiving output values of the registers 1-n of the platform to be verified, judging whether the output values of the registers 1-n are equal or not, and if the output values of the registers 1-n are equal, passing the verifying step; defining binary system value data; adding 1 to the lowest order of data by each system clock, giving each order of n orders of the data to the registers 1-n respectively, outputting a vote output result on a falling edge of each system clock by the platform to be verified according to values of the registers 1-n of a rising edge of each system clock; calculating the number of all the registers of which a register value is 1 and 0 in each system clock, if the number of the registers of which the register value is 1 is more, making a is equal to1, and if the number of the registers of which the register value is 0 is more, making a is equal to 0; detecting whether the vote output result of the platform to be verified is equal to a or not, and if the vote output result of the platform to be verified is equal to a namely the value of the most quantity, passing the verifying step.
Owner:BEIJING INST OF COMP TECH & APPL
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