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Nios II soft-core based high-speed 1553B communication equipment simulator on missile

A technology of communication equipment and simulator, which is applied in the direction of data exchange through path configuration, digital transmission system, electrical components, etc. It can solve the problem of increased system size, code rate that cannot meet the real-time requirements of system data transmission, and insufficient flexibility in use, etc. problem, to achieve the effect of improving real-time performance, reducing design cost, and avoiding missile damage

Inactive Publication Date: 2012-06-13
HARBIN INST OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The purpose of the present invention is to provide a kind of high-speed 1553B communication equipment simulator based on Nios II soft core, it can not satisfy the real-time requirement of system data transmission and the high-speed 1553B chip needs separate CPU to control in order to solve the code rate of 1Mbps , so that the volume of the system increases and the problem of not being flexible enough to use

Method used

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  • Nios II soft-core based high-speed 1553B communication equipment simulator on missile
  • Nios II soft-core based high-speed 1553B communication equipment simulator on missile
  • Nios II soft-core based high-speed 1553B communication equipment simulator on missile

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specific Embodiment approach 1

[0011] Specific implementation mode 1. Combination figure 1 This embodiment is specifically described. This embodiment includes a communication simulator 20, and the communication simulator 20 includes a sending FIFO module 2, a first Manchester encoder 3, a first redundant channel 4, a second redundant channel 7, and a second Manchester encoding device 8, receiving FIFO module 9, dual-port RAM module 10, control register 11, protocol processing unit 12, clock reset unit 13, EPCS module 14, FLASH module 15, SRAM module 16, communication simulator bus 17, 1553B bus 18 and FPGA module 19, the present invention also includes Nios II soft-core module 1, channel bus analog receiver 5 and channel bus analog transmitter 6,

[0012] The first signal output end of the Nios II soft core module 1 is connected to the first signal receiving end of the sending FIFO module 2, and the signal output end of the sending FIFO module 2 is connected to the signal receiving end of the first Manchest...

specific Embodiment approach 2

[0027] Specific embodiment two, combine Figure 5 Describe this embodiment in detail. The difference between this embodiment and the first embodiment is that the channel bus analog receiver 5 includes a first diode 5-1, a second diode 5-2, and a third diode 5- 3. The fourth diode 5-4, the first operational amplifier 5-5, the second operational amplifier 5-6, the first R 1 Resistor 5-7, the first R 2 resistors 5-8 and transformers 5-9,

[0028] The cathode of the first diode 5-1 is connected to +3.3V, and the anode of the first diode 5-1 is connected to the cathode of the second diode 5-2 and the first operational amplifier 5-5 at the same time. The signal output terminal is connected, the signal output terminal of the first operational amplifier 5-5 is connected to the terminal +rx, the anode of the second diode 5-2 is grounded, and the positive electrode of the dual-phase power supply of the first operational amplifier 5-5 The terminal is connected to +5V, the negative ter...

specific Embodiment approach 3

[0031] Specific embodiment three, combine Image 6 This embodiment is described in detail. The difference between this embodiment and the first embodiment is that the channel bus analog transmitter 6 includes a second R 1 Resistor 6-1, the third R 1 Resistor 6-2, first triode 6-3, second triode 6-4, R3 resistor 6-5, fifth diode 6-6, sixth diode 6-7, second R 2 Resistors 6-8, the third R 2 resistors 6-9, transformers 6-10,

[0032] The second R 1 One end of resistor 6-1 is connected to terminal +tx, the second R 1 The other end of the resistor 6-1 is connected to the base of the first triode 6-3, and the collector of the first triode 6-3 is connected to the anode of the fifth diode 6-6 and the second R 2 One end of the resistor 6-8 is connected, and the emitter of the first triode 6-3 is connected to R 3 One end of the resistor 6-5 is connected to the emitter of the second triode 6-4, and the terminal -tx is connected to the third R 1 One end of resistor 6-2 is connected...

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Abstract

The invention relates to a Nios II soft-core based high-speed 1553B communication equipment simulator on a missile, which aims to solve the problems that existing bit rate cannot meet the requirement of real-time data transmission, size is large, power consumption is high and flexibility in use is poor. The Nios II soft-core based high-speed 1553B communication equipment simulator comprises an existing communication equipment simulator, a Nios II soft-core module, a channel bus simulation receiver and a channel bus simulation transmitter, signals of the Nios II soft-core module are transmitted to a Manchester encoder through an FIFO (first in first out) transmission module, are transmitted to a 1553B bus through a redundancy channel and the channel bus simulation receiver, the 1553B bus is connected with the channel bus simulation transmitter and transmits the signals to a signal input end of an FIFO receiving module through the redundancy channel and the Manchester encoder and then outputs to a signal receiving end. The Nios II soft-core based high-speed 1553B communication equipment simulator is applicable to high-speed communication.

Description

technical field [0001] The invention relates to a 1553B communication equipment simulator. Background technique [0002] MIL-STD-1553B is a time-division command / response multiplex data bus inside the aircraft, and it is also widely used in various types of missiles. 1553B bus is the abbreviation of MIL-STD-1553B bus, where B is BUS. The standard code rate of the 1553B bus is 1Mbps, that is, 10 bits per second. 6 bit. However, with the continuous improvement of missile performance, its requirements for communication speed are also getting higher and higher, and the code rate of 1Mbps can no longer meet the real-time requirements of system data transmission. In the debugging and verification stage, the missile automatic test system needs to be docked with the equipment on the missile. Repeated testing of the real equipment on the missile may damage the equipment on the missile, and the real equipment cannot simulate various failure states, so it is necessary to develop a ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L29/06H04L29/08H04L12/40H04L12/24
Inventor 许永辉魏长安宋升金杨京礼钱科威姜守达
Owner HARBIN INST OF TECH
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