Verifying method and apparatus for FPGA boundary scan system

Abstract

The invention provides a verifying method and apparatus for an FPGA (Field-Programmable Gate Array) boundary scan system, which are used for debugging the FPGA boundary scan system on a simulation platform. The method includes the following steps: verifying the simulation characteristics of an IO module of an FPGA through an input instruction / output instruction, wherein the verifying step includes verifying the input characteristics of the IO module and verifying the output characteristics of the IO module; verifying instruction processing of the boundary scan system, wherein instructions include a sampling input instruction, an output test instruction, an output enhancement test instruction and an output training test instruction; and verifying internal connection of the boundary scan system and the FPGA through an internal test instruction, wherein a round trip pathway of the FPGA is gated through user configuration. The verifying method and apparatus can comprehensively and thoroughly verify the FPGA boundary scan system and ensure correctness of functions of the FPGA boundary scan system.

Description

technical field [0001] The present invention relates to the technical field of ultra-large-scale programmable integrated circuits, in particular to a verification method and system for a Field-Programmable Gate Array (FPGA: Field-Programmable Gate Array) boundary scan system. Background technique [0002] With the emergence of large-scale integrated circuits, the manufacturing process of printed circuit boards has become small, micro, and thin. Traditional information and communication technology (ICT: Information Communication Technology) testing has no way to meet the testing requirements of such products. Many, the components are small in size, and the density of the board is particularly high. There is no way to perform the probe test at all, so the Joint Test Action Group (JTAG, JointTestActionGroup) boundary scan system came into being. The method of embedding the boundary scan system in the FPGA circuit design can solve the difficult problem of FPGA chip problem locat...

AI Technical Summary

Problems solved by technology

[0004] Although the FPGA boundary scan system can diagnose the faults when the chip is working, the correctness of the design of the FPGA boundary scan system itself cannot be fully guaranteed, which leads to the problem of inaccurate measurement of the chip

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