Data network design verification method and device and verification equipment

Abstract

The invention provides a data network design verification method and device and verification equipment. The data network design verification method comprises the following steps: constructing a data transmission layer model for a tested data network function module; arranging a chip design function unit in the data transmission layer model to construct a data bus system; and performing data transmission verification on the data bus system based on the first test sequence. The chip design function unit comprises a clock domain crossing interface module, a voltage domain crossing interface module or a relay unit.

Description

technical field [0001] Embodiments of the present disclosure relate to a data network design verification method, device and verification equipment. Background technique [0002] As the complexity of digital integrated circuit systems continues to increase, the types and numbers of functional modules that make up System-on-a-Chip (SoC) are also increasing, and the data interaction network between modules in the system is also becoming more and more complex. more and more complicated. In order to quickly adapt to different system applications and integration requirements, the network-on-chip data bus with scalable parameters and reconfigurable topology is often used in current large-scale integrated systems. At present, the verification process of the on-chip data network in large-scale integrated circuits usually adopts the method of separately verifying the module level and the system level. However, the module-level verification cannot be guaranteed to be consistent with...

AI Technical Summary

Problems solved by technology

However, the verification at the module level cannot be guaranteed to be consistent with the actual chip design scenario, so the verification is not sufficient

For system-level verification, due to the complexity of integrated circuits, there are inevitably problems such as long simulation time and limited verification scenarios.

Images