SOC (System on a Chip) debugging and verifying device and method

Abstract

The embodiment of the invention discloses an SOC (System on a Chip) debugging and verifying device and method, relating to the field of SOCs. The SOC debugging and checking device realizes sufficient verification on an IP hardcore and an SOC, greatly increases the developing efficiency of SOC products and lowers the developing cost. The SOC debugging and verifying device is in bus connection with an FPGA (Field Programmable Gate Array) platform, and the SOC debugging and verifying are carried out through the bus connection. The SOC debugging and verifying device and method are applied to SOC verifying.

Description

technical field [0001] The present invention relates to the field of system on chip (System on Chip, hereinafter referred to as SOC), and in particular to an SOC debugging verification device and method. Background technique [0002] In the early stage development of SOC chip, the debugging verification of the system is the key to whether the chip can be successfully developed. A complex SOC system consists of numerous IP modules, and each module must participate in the verification of the entire system. During the preliminary verification of the SOC chip, the soft core method is generally used to synthesize each IP module and load it into the field-programmable gate array (Field-Programmable Gate Array, hereinafter referred to as FPGA) platform. [0003] Due to the confidentiality of IP modules and the cooperation between manufacturers, it is generally difficult to obtain soft cores from IP manufacturers in the early stage of work; in addition, the resources of the FPGA pl...

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Problems solved by technology

[0003] Due to the confidentiality of IP modules and the cooperation between manufacturers, it is generally difficult to obtain soft cores from IP manufacturers in the early stage of work; in addition, the resources of the FPGA platform are limited, and the addition of new IP systems sometimes causes system resources to Insufficient situation, these two situations, often hinder the progress of development and reduce the efficiency of development

[0004] In view of this problem, at present, in the early verification and debugging of SOC chips, when integrating IP modules, a new FPGA platform with larger resources is generally replaced, and the risk of IP quality increases to a large extent. The development cost of the SOC chip

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