Control method and device for write protection in embedded system
An embedded system, write protection technology, applied in the direction of preventing unauthorized use of memory, etc., can solve the problem of low security, achieve the effect of improving security, facilitating program error location and processing, and low application cost
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Embodiment 1
[0042] Figure 4 It is a preferred flow chart of a control method for write protection in an embedded system according to an embodiment of the present invention, which includes the following steps:
[0043] S401. Obtain an illegal write address to be written by a write instruction that causes an abnormal interruption of the CPU bus, wherein the illegal write address is preset as write protection;
[0044] S402, modifying the illegal write address to an address of a write-allowed area;
[0045] S403. Execute a write command operation on the address of the write-allowed area.
[0046] In this embodiment, the write command that requires the illegal write address is executed by modifying the illegal write address to the address of the area that allows writing, so that the control of write protection does not depend on the device driver interface and CPU provided by the operating system. (central processing unit) MMU (memory management unit) function, special hardware write prote...
Embodiment 2
[0056] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments. Take the CPU of the 32-bit RISC instruction set commonly used in the embedded system of network communication equipment, the communication processor MPC860 series of Freescale (Freescale) Company as an example.
[0057] Such as Figure 5 shown, including the following steps:
[0058] Step S501 , determining the entry address of the bus exception interrupt processing of the CPU. According to the chip description in the MPC860 user manual, the interrupt vector offset address for MPC860 processing bus exceptions is 0x00200 (see chapter 7.1.2.2 of the user manual): Machine Check Interrupt. The machine check interrupt is enabled by setting MSR[ME] (MSR: ME bit of the machine status register). The reason is generally that the access address does not exist or a data error occurs, and writing to the bus protected area will also generate an interrupt....
Embodiment 3
[0069] Figure 8 It is a preferred structural diagram of a control device for write protection in an embedded system according to an embodiment of the present invention, which includes: an acquisition unit 801, configured to acquire an illegal write address to be written by a write instruction that causes an abnormal interruption of the CPU bus, wherein, The illegal write address is preset as write protection; the modification unit 802 is used to modify the illegal write address to the address of the area that allows writing; the execution unit 803 is used to execute the write instruction to the address of the area that allows writing operate.
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