Method and circuit for scheduling data of memory through fast Fourier transform (FFT) reverse operation

Abstract

The invention discloses a method and a circuit for scheduling the data of a memory through fast Fourier transform (FFT) reverse operation. Two N/2 depth single-port memories are used for data scheduling, so that the area and power consumption advantages of the single-port memories are fully exerted, and the area of an on-chip memory is effectively reduced; a uniform data pause signal and a direct write after read strategy are adopted, so that the pause of external data can be waited while the data is not lost and a read and write time sequence is not influenced through the design; and N clock data delays with a fixed rule are adopted, so that detection logic that the shortest delay time is realized by a large first in first out (FIFO) memory is effectively avoided. The method and the circuit are high in configurability and expandability, and the dependence of different point numbers on memory capacity and control logic is furthest avoided; and compared with the conventional reverse operation method, the method has the advantages that: a few resources are occupied, configuration flexibility is high, and interrupted and paused continuous data stream can be processed.

Description

technical field [0001] The invention belongs to the field of Very Large Scale Integrated Circuit (VLSI, Very Large Scale Integrated Circuit), and specifically relates to a memory data scheduling method and a circuit structure of Fast Fourier Transform (FFT, Fast Fourier Transform) reverse operation. Background technique [0002] With the increasing demand for applications such as radar, satellite, and consumer electronics, the number of points and precision requirements for FFT processor design are increasing. The pipeline structure is flexible and configurable, and it is widely used as an important means to improve the calculation speed. In the FFT calculation of the floating-point data format with large numbers, the area and performance of the inversion module have a crucial impact on the performance of the entire FFT processor, so it is necessary to develop a method that can efficiently complete the inversion operation and have a lower area overhead Reverse module memory ...

AI Technical Summary

Problems solved by technology

[0017] In 1994, Wen-Zen Shen used a dual-port memory to implement a 504=7 ×8×9 Prime Factor Algorithm (PFA, Prime Factor Algorithm) data reordering, but its algorithm and data scheduling are very complicated, and it is not easy to expand and apply to data reordering of various configurable FFT points

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