Latching amplification circuit applied to memory and reading method
A technology for amplifying circuits and memory, applied in static memory, digital memory information, information storage, etc., can solve problems such as power consumption, and achieve the effects of reducing power consumption, saving power, and reducing power
Active Publication Date: 2014-05-21
SEMICON MFG INT (SHANGHAI) CORP +1
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This will consume a lot of power when reading the data stored in each storage unit
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[0047] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and examples.
[0048] It can be seen from the prior art that when reading the data stored in each memory cell whose memory cell area is located on the same local bit line, during the entire read process, the large circuit for latching and storing needs to apply current, so this will consume a lot of energy. of electric energy. However, in the whole reading process, the lock storage circuit first needs to apply current to the local bit line to charge each memory cell on the local bit line. After a period of time, each memory cell on the local bit line will be The level signal is fed back to the lock storage circuit through the local bit line. At this time, the lock storage circuit starts to work, and the processed level signal that has been amplified and latched is pro...
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The invention discloses a latching amplification circuit applied to a memory and a reading method. The circuit comprises a plurality of latching modules for a local bit line and an amplification module for a global bit line, wherein the latching modules for the local bit line are used for charging storage units on the local bit line through the local bit line according to applied pre-charging pulse signals, and sending received level signals to the amplification module for the global bit line according to applied control signals until the level signals are fed back by the storage units on the local bit line through the local bit line; the fed-back level signals are used for indicating data which is stored in the storage units; the amplification module for the global bit line is used for receiving the level signals, which are sent by the latching modules for the local bit line, of the storage units through the global bit line, and outputting the level signals to external equipment after amplification and latching. When the data, which is stored in the storage units, is read by the latching amplification circuit, the electric energy consumption is reduced.
Description
technical field [0001] The invention relates to the technical field of semiconductors, in particular to a lock storing large circuit and a reading method applied in a memory. Background technique [0002] For the memory in the semiconductor device, it includes the peripheral circuit area and the memory cell area, wherein there are a plurality of memory cells in the memory cell area, and the plurality of memory cells are arranged in parallel in the Y-axis direction and the X-axis direction. The line is connected to the peripheral circuit area, and is connected to the peripheral circuit area through the word line in the X-axis direction. The word line is used to select the memory cell, and the local bit line is used to read the data stored in the selected memory cell. [0003] Specifically, in the memory cell area, after the current is applied through the local bit line, the memory cell feedback level signal indicates the stored data, for example, a high level signal indicates...
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IPC IPC(8): G11C7/06
Inventor 權彝振杨家奇许家铭郑晓
Owner SEMICON MFG INT (SHANGHAI) CORP