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Instruction transmission control method and device based on instruction block and processor

An instruction issue and control method technology, applied in the computer field, can solve problems such as poor pipeline performance, inability to explore the independency of instructions before and after launch conditions, and achieve the effects of good performance, balancing complexity and efficiency, and good complexity and efficiency.

Active Publication Date: 2014-12-24
JIANGNAN INST OF COMPUTING TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although the sequential launch mechanism is relatively simple, the launch conditions are too limited to discover the irrelevance between previous and subsequent instructions, resulting in poor pipeline performance

Method used

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  • Instruction transmission control method and device based on instruction block and processor
  • Instruction transmission control method and device based on instruction block and processor

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Embodiment Construction

[0024] In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be described in detail below in conjunction with specific embodiments and accompanying drawings.

[0025]

[0026] figure 1 A flowchart schematically shows a method for controlling instruction issuance based on instruction blocks according to a preferred embodiment of the present invention.

[0027] First, some terms in this specification are explained, so that the present invention can be better understood. The term "instruction block" is a concept in the dynamic running state of a program executed by a processor, specifically, the term "instruction block" refers to an instruction sequence separated by barrier instructions during operation. The dynamic operation of the entire program can be divided into multiple instruction blocks. The term "fence instruction" refers to an instruction that changes the direction of instruction flow; for e...

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Abstract

The invention provides an instruction transmission control method and an instruction transmission control device based on an instruction block, and a processor. The instruction transmission control method comprises the steps of: judging the instruction type of an instruction in an instruction ready transmission state, if the instruction in the instruction ready transmission state is a barrier instruction, further judging a transmission condition, if the instruction to be executed much earlier cannot be transmitted, preventing the instruction in the instruction ready transmission state as the barrier instruction from being transmitted, if the instructions to be executed much earlier can be emitted or have been transmitted, transmitting the instruction in the instruction ready transmission state as the barrier instruction, if the instruction in the instruction ready transmission state is judged to be a common instruction, further judging the transmitting condition, if the barrier instruction to be executed much earlier is not transmitted, preventing the instruction in the instruction ready transmission state as the common instruction from being transmitted, if no barrier instruction to be executed much earlier is not transmitted, transmitting the instruction in the instruction ready transmission state as the common instruction.

Description

technical field [0001] The present invention relates to the field of computer technology, more specifically, the present invention relates to an instruction block-based instruction emission control method and an instruction emission control device, and the present invention also relates to an instruction block-based instruction emission method or device processor. Background technique [0002] Modern processors generally use pipeline technology to increase the processing speed of the processor. Pipeline technology refers to a quasi-parallel processing implementation technology in which multiple instructions overlap and operate during program execution. More specifically, the pipeline technology divides an instruction execution process into multiple stages, wherein different instructions are executed in different stages, so as to realize instruction parallelism, thereby improving the processing speed of the processor. [0003] Existing processor pipeline launch mechanisms m...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/30G06F9/38
Inventor 李宏亮过锋高红光许勇郑方唐勇任秀江
Owner JIANGNAN INST OF COMPUTING TECH
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