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Method for positioning logic fault

A logic fault, fault technology, applied in the direction of measuring devices, instruments, measuring electricity, etc., can solve the problem of inability to accurately locate the chip and so on

Active Publication Date: 2015-07-22
常熟高新技术创业服务有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0013] The problem to be solved by the present invention: the traditional test fault diagnosis method cannot accurately locate the specific module in the chip

Method used

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  • Method for positioning logic fault
  • Method for positioning logic fault

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Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0027] Concrete implementation steps of the present invention are as follows:

[0028] Step 1: Add 8 binary selectors to the bottom module, and select and control the 8 scan chains in this module.

[0029] Step 2: The bottom module of the chip has 8 scan chains, and each macro module part has 8 rows and 8 columns of 64 bottom modules, which is regarded as an 8*8 array, and all the bottom modules in the macro module part are multiplexed, and at the same time A decoder is added to the macro module to control the working status of the 8-bit, that is, the 8-line bottom module;

[0030] Step 3: When scanning the design, control the opening of a row of bottom-layer modules through the configuration decoding output each time (that is, the row of the positioning array), and the remaining 7 rows of 56 bottom-layer modules are all bypassed by the two-to-one selector. The test vector generated at this time It is the underlying module used to scan and test this row.

[0031] Step 4: Dur...

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PUM

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Abstract

The invention discloses a method for positioning a logic fault and relates to the technical field of an integrated circuit. In order to solve the problem that the fault of a register unit of a specific module in a chip cannot be accurately positioned according to the traditional test fault diagnosis method, 8 scanning chains are arranged on a bottom module of the chip; 64 bottom modules in 8 lines and 8 rows are arranged on each region part; the 64 bottom modules can be regarded as a 8*8 array; at a test moment, scanning ports si1-si8 are parallel in the scanning chains for scanning and testing; once the fault occurs, a certain row of fault information is displayed in a scanning test result log file; and according to an array coordinate principle, a point in the array can be positioned so long as an accurate coordinate is obtained, and the specific module in the chip can be accurately positioned, so that the positioning for the logic fault is realized and the cost of the chip is lowered.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a logic fault location method. Background technique [0002] With the rapid development of the scale of integrated circuits, the logical structure is becoming more and more complex, and the integration of chips is continuously improving. [0003] As well as the continuous improvement of the process level, the chip is facing more and more testing challenges at the chip level and system level. At this time [0004] Early classic testing means and methods have been unable to meet the requirements. In addition, with the continuous improvement of integrated circuit clock frequency [0005] The number of gates integrated with input and output pins is increasing. In the past, the integrated circuit was solved simply from the perspective of improving test equipment. [0006] The problem of testing has been unable to meet the needs of the development of integrated circuits,...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/3177
Inventor 张震戚湧方赓
Owner 常熟高新技术创业服务有限公司