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Method for positioning logic fault

A logic fault and fault technology, applied in the direction of measuring devices, instruments, measuring electronics, etc., can solve problems such as inability to accurately locate register units, loss, and unrepairable chips

Active Publication Date: 2012-12-26
常熟高新技术创业服务有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The problem to be solved by the present invention: the traditional test fault diagnosis method cannot accurately locate the failure of the register unit of the specific module in the chip, which brings certain challenges to the redundancy repair work, and therefore may make some chips irreparable and become useless. piece, causing loss

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Experimental program
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Embodiment Construction

[0012] Concrete implementation steps of the present invention are as follows:

[0013] Step 1: Add 8 alternative selectors in the bottom module, and select and control the 8 scan chains in the module.

[0014] Step 2: multiplex all the underlying modules in the macromodule part, and add a decoder to the macromodule part to control the working status of the 8-bit, ie, 8-line, bottom-layer modules.

[0015] Step 3: When scanning the design, control the opening of a row of bottom-level modules by configuring the decoding output each time (that is, the row of the positioning array), and the remaining 7 rows of 56 bottom-level modules are all bypassed by the two-to-one selector. The test vector generated at this time It is the underlying module used to scan and test this row.

[0016] Step 4: During the scan test, the test vectors input in parallel by the scan input port (si1-si8) only pass the test of one line. If there is a fault in this line, it can be displayed in the fault fi...

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Abstract

The invention discloses a method for positioning a logic fault and relates to the technical field of an integrated circuit. In order to solve the problem that the fault of a register unit of a specific module in a chip cannot be accurately positioned according to the traditional test fault diagnosis method, 8 scanning chains are arranged on a bottom module of the chip; 64 bottom modules in 8 lines and 8 rows are arranged on each region part; the 64 bottom modules can be regarded as a 8*8 array; at a test moment, scanning ports si1-si8 are parallel in the scanning chains for scanning and testing; once the fault occurs, a certain row of fault information is displayed in a scanning test result log file; and according to an array coordinate principle, a point in the array can be positioned so long as an accurate coordinate is obtained, and the specific module in the chip can be accurately positioned, so that the positioning for the logic fault is realized and the cost of the chip is lowered.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a logic fault location method. Background technique [0002] With the rapid development of the scale of integrated circuits, the logic structure is becoming more and more complex, the integration level of the chip is constantly improving, and the process level is constantly improving, so that the chip is facing more and more testing challenges at the chip level and system level. At that time, the classic testing methods and methods in the early days could no longer meet the requirements. In addition, with the continuous improvement of integrated circuit clock frequency and the increasing number of integrated gates of input and output pins, the previous solution to the problem of integrated circuit testing from the perspective of improving test equipment can no longer meet the needs of integrated circuit development. It is recognized that testing is no longer simply a...

Claims

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Application Information

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IPC IPC(8): G01R31/3177
Inventor 张震戚湧方赓
Owner 常熟高新技术创业服务有限公司