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Clock synchronization method and master-slave clock entity

A clock synchronization and clock technology, which is applied in the field of transmission network, can solve problems such as inability to synchronize the master clock and errors in the Offset value

Active Publication Date: 2015-04-01
DATANG MOBILE COMM EQUIP CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Therefore, after substituting the above t1, t2, t3, and t4 into the formula (1), the obtained Offset value will have errors, and the slave clock cannot synchronize with the master clock by using this Offset value

Method used

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  • Clock synchronization method and master-slave clock entity
  • Clock synchronization method and master-slave clock entity
  • Clock synchronization method and master-slave clock entity

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Embodiment Construction

[0075] A method for detecting delay of an SDH network element and an SDH network element provided by an embodiment of the present invention are introduced below.

[0076] image 3 The flow chart of the embodiment of the SDH network element delay detection method is shown, as shown in the figure:

[0077] Step 301: Detect the moment when the frame header of the E1 frame on the PDH interface of the SDH network element flows out and the moment when the frame header of the SDH frame flows in on the SDH interface; or detect the moment when the frame header of the SDH frame on the SDH interface of the SDH network element flows out and the PDH The moment when the frame header of the E1 frame flows in on the interface.

[0078] SDH network element equipment with an SDH interface on one side and a PDH interface on the other. For the direction of inflow as PDH interface and outflow as SDH interface, you can detect the frame header time of the E1 frame flowing in from the PDH interface,...

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Abstract

The embodiment of the invention discloses a clock synchronization method, which comprises the following steps that a slave clock marks a timestamp on a frame header of a frame received after a first message to be used as t2; the slave clock receives a second message including t1 sent by a master clock, wherein t1 is a timestamp on the frame header of one frame after the first message sent by the master clock, and the sequence of frames time stamped by the master clock after sending the first message is the same as that of frames time stamped by the master clock after sending the first message; the slave clock sends a third message to the master clock, and time stamps a frame header of one frame after the third message to be used as t3; the slave clock receives a fourth message including t4 from the master clock, wherein t4 is a timestamp on a frame header of one frame received by the master clock after the third message; the slave clock uses t1, t2, t3 and t4 to calculate to obtain Offset; and the self clock is adjusted in accordance with Offset.

Description

[0001] This application is a divisional application, its parent case is application number 200810057606.3, the application date is February 3, 2008, and the name is "SDH network element delay detection method, clock synchronization method, master-slave clock entity and SDH network element" invention patent applications. technical field [0002] The invention relates to the technical field of transmission network, in particular to a clock synchronization method and a master-slave clock entity. Background technique [0003] The purpose of synchronization is to keep two or more clocks at the same time. Clock synchronization methods include master-slave synchronization. In this way, the timing signal is transmitted from the master clock to the subordinate slave clock, and the slave clock adjusts its own clock according to the obtained timing signal to maintain synchronization with the master clock. [0004] In the clock synchronization method of a master-slave synchronization ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04J3/06
Inventor 谢子阳
Owner DATANG MOBILE COMM EQUIP CO LTD
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