Non-buried layer double deep N well high-voltage isolation N-type LDMOS and method for manufacturing N-type LDMOS devices

A high-voltage isolation, N-type technology, used in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as cost increase, and achieve the effect of cost reduction, easy implementation, and performance improvement

Active Publication Date: 2015-04-08
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, this method leads to a substantial increase in cost

Method used

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  • Non-buried layer double deep N well high-voltage isolation N-type LDMOS and method for manufacturing N-type LDMOS devices
  • Non-buried layer double deep N well high-voltage isolation N-type LDMOS and method for manufacturing N-type LDMOS devices

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Embodiment Construction

[0025] Such as figure 2 As shown, the double-deep N-type well high-voltage isolation N-type LDMOS device of the non-buried layer of the embodiment of the present invention includes: an N well 11 is provided on a P-type silicon substrate 10, and a P well 12 and a plurality of Isolation structure 13; above the N well 11 is a gate 14, one end of the gate 14 is located above the P well 12, and the other end is located above the isolation structure 13; there is an N-type heavily doped region 152 in the N well 11, and the N-type heavy The doped region 152 serves as the drain of the LDMOS device, the P well 12 has an N-type heavily doped region 151, and the N-type heavily doped region 151 serves as the source of the LDMOS device; there is a first deep N-type well below the P well 12 191, there is a second deep N-type well 192 under the N-type heavily doped region 152, and the depth and implantation concentration of the first deep N-type well 191 and the second deep N-type well 192 a...

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Abstract

The present invention discloses a non-buried layer double deep N well high-voltage isolation N-type LDMOS. A first deep N well is arranged on a P-type silicon substrate; and a P well and a plurality of isolation structures are arranged in the first deep N well. A gate is arranged on the deep N well; and one end of the gate is located on the P well, while the other end of the gate is located on an isolation structure. An N-type heavily doped region is arranged in the first deep N well, and the N-type heavily doped region is a drain for an LDMOS device; and an N-type heavily doped region is arranged in the P well, and the N-type heavily doped region is a source for the LDMOS device. A second deep N well is arranged below the P well; a third deep N well is arranged below the N-type heavily doped region in the first deep N well, and the depth and the injection concentration of the second and the third deep N wells are greater than those of the first deep N well. The present invention also discloses a method for manufacturing N-type LDMOS devices. The method of the present invention enables separate control of PNP punch through in the vertical direction and optimization of a withstand voltage of a horizontal drain drift and Rdson; and the process is simple and flexible, easy to implement, and dramatically reduced in costs compared to a buried layer + epitaxial process .

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to a non-buried double-deep N-well high-voltage isolation N-type LDMOS. The invention also relates to the manufacturing method of the double-deep N-type well high-voltage isolation N-type LDMOS of the non-buried layer. Background technique [0002] High-voltage isolated N-type LDMOS devices are widely used in the design of power management chips due to their flexible design, low ratio of on-resistance (Rdson), and fast response speed. Compared with ordinary N-type LDMOS devices, isolated N-type LDMOS devices will perform deep N-type well (Deep N well, DNW) implantation under its P-type well (P body), such as figure 1 shown for isolation purposes. Therefore, the potential connected to the source (Source, N+) of the isolated N-type LDMOS and the lead-out terminal (Bulk) of the P-type well can be connected at the potential of 0 potential (ground) and the drain (Drain)...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/06H01L21/336
Inventor 刘剑段文婷孙尧陈瑜陈华伦
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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