ldpc encoder and encoding method in cmmb based on block-column cycle
An LDPC code and encoder technology, applied in the field of efficient implementation of LDPC encoders, can solve problems such as high cost, high power consumption, and large storage capacity.
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[0020] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.
[0021] A regular LDPC code can be defined by a parameter set (n, ρ, λ), where n is the code length, ρ and λ are the row weight and column weight of the parity check matrix H, respectively. The LDPC code satisfies the following relationship:
[0022] Hc T =0 (1)
[0023] where superscript T Indicates the transpose, 0 is an all-zero vector (or matrix), and c is the following 1×n order codeword
[0024] c=[c i ] (2)
[0025] Among them, 0≤i
[0026] For LDPC codes in systematic form, H can be transformed into figure 1 The approximate lower triangular shape H shown ALT . In the figure, k is the number of information bits, r is the number of parity bits, and they satisfy k+r=n. It can be seen from the figure that the H ALT Divided vertically into 4 parts
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