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Delta-sigma fractional-N frequency synthesizer with binary-weighted digital-to-analog differentiators for canceling quantization noise

A technology of quantizer and differentiator, applied in automatic power control, electrical components, etc., can solve problems such as complex DAC design

Inactive Publication Date: 2013-05-01
MICROCHIP TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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However, it requires additional digital signal

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  • Delta-sigma fractional-N frequency synthesizer with binary-weighted digital-to-analog differentiators for canceling quantization noise
  • Delta-sigma fractional-N frequency synthesizer with binary-weighted digital-to-analog differentiators for canceling quantization noise
  • Delta-sigma fractional-N frequency synthesizer with binary-weighted digital-to-analog differentiators for canceling quantization noise

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[0027] A delta-sigma fractional-N frequency synthesizer with a digital-to-analog differentiator that eliminates quantization noise optimizes phase noise for wideband systems.

[0028] The present invention provides methods and systems for removing spurious spurs in delta-sigma fractional-N synthesizers by applying an amplitude modulated pulse error signal. False spurs originate from excessive time intervals at the input of the phase comparator, which is quantization noise in fractional-N synthesizers. Quantization noise can be obtained by comparing the input and output of delta-sigma modulation. By applying the inverse of this known noise as the error signal, spurious spurs can be removed. Although the noise is zero-averaged and high-pass shaped by the delta-sigma modulator, residual noise is still significant in wideband signal systems. False spurs are minimized by adding an amplitude modulated pulse error signal to the output of the charge pump.

[0029] The present inven...

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Abstract

A phase lock loop includes a quantization circuit that generators an out of phase noise cancellation signal from an error in a delta-sigma modulator and applies the noise cancellation signal to the charge pump. The quantization circuit includes a digital-to-analog differentiator. The digital-to-analog differentiator may be, for example, a single-bit first-order digital-to-analog differentiator, a single-bit second-order digital-to-analog differentiator, or a full M-bit binary-weighted digital to analog differentiator.

Description

technical field [0001] The present invention relates to delta-sigma fractional-N frequency synthesizers, and more particularly to delta-sigma fractional-N frequency synthesizers including digital-to-analog differentiators. Background technique [0002] Many circuits use phase-locked loops to generate frequency signals. In integer-N PLL architectures (such as the following combined figure 1 As described), the phase-locked loop includes a phase-frequency detector, a charge pump, a loop filter, and a voltage-controlled oscillator (VCO) connected in series to provide a frequency signal. The frequency signal is fed back through an integer divider to provide a feedback signal to the phase frequency detector. This architecture has small reference spurs, but coarse frequency resolution and long frequency lock times. For some applications (eg, wireless communication standards), this architecture is inflexible. [0003] Fractional-N PLL architectures (such as the following in conj...

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Application Information

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IPC IPC(8): H03L7/197
CPCH03L7/1976H03L7/197
Inventor 恒瑜·江徐志伟吴逸诚茂聪·弗兰克·张
Owner MICROCHIP TECH INC