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Debug system, electronic control unit, information processing unit, semiconductor package, and transceiver circuit

A technology of electronic control unit, transceiver circuit, applied in the technical field used by information processing unit, capable of solving problems such as error control

Inactive Publication Date: 2013-05-22
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] The above technique described in Japanese Unexamined Patent Publication No. Hei 9(1997)-44372 prevents a control target from being erroneously controlled due to an error in communication between an electronic control unit and the controller

Method used

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  • Debug system, electronic control unit, information processing unit, semiconductor package, and transceiver circuit
  • Debug system, electronic control unit, information processing unit, semiconductor package, and transceiver circuit
  • Debug system, electronic control unit, information processing unit, semiconductor package, and transceiver circuit

Examples

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no. 1 example

[0035] figure 1 is a block diagram illustrating a configuration of a debugging system 1 for developing an information processing unit provided by the present invention. Used when testing before an engine, etc. to be developed is installed in an actual vehicle (full vehicle) figure 1 The system configuration shown in . refer to figure 1, a debugging system 1 for testing an engine before it is installed in an actual vehicle includes an engine test bench room 2 and a test control room 3 . The engine test bench room 2 includes an engine (control object) 4 and an ECU (electronic control unit) 5 . The test control room 3 includes external units 6 and a host computer 7 for development.

[0036] Such as figure 1 As shown in , the engine test bench chamber 2 is coupled to the test control chamber 3 using long distance wires 8 . Data for commissioning and measurements are exchanged via long-distance conductors 8 . In the first embodiment, the ratio of the distance between the eng...

no. 2 example

[0060] A second embodiment of the present invention will now be described. Figure 5 is a block diagram illustrating the configuration of the debugging system 1 according to the second embodiment. Such as Figure 5 As shown in , the debug system 1 according to the second embodiment is configured such that the transceiver circuit 13 is arranged outside the ECU 5 . When the ECU 5 is provided as a case, the ECU case accommodates various devices including the target microcomputer 12 . Such an ECU case may not be able to provide an installation space for the transceiver circuit 13 for communication.

[0061] The debug system 1 according to the second embodiment is configured such that the transceiver circuit 13 is arranged as an external part to solve the above problems. Since the target microcomputer 12 is located at a distance from the transceiver circuit 13, an increased burden can be placed on the target microcomputer 12 to maintain the performance of the communication. How...

no. 3 example

[0064] A third embodiment of the present invention will now be described. Figure 6 is a block diagram illustrating the configuration of the debugging system 1 according to the third embodiment. In the debugging system 1 according to the third embodiment, the target microcomputer 12 installed in the ECU 5 is formed of a SIP (System in Package). Such as Figure 6 As shown in , the microcomputer chip 15 in the target microcomputer 12 according to the third embodiment is formed of a single semiconductor device (IC chip). Similarly, the transceiver circuit chip 16 is formed of a single semiconductor device (IC chip), which is separate from the microcomputer chip 15 .

[0065] In the debugging system 1 according to the third embodiment, the target microcomputer 12 is provided as a SIP. Therefore, it is not necessary to perform a process of sealing the transceiver circuit chip 16 into another package. In addition, the configuration employed in the third embodiment enables the mi...

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PUM

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Abstract

Disclosed is a debug system that suppresses the supply of extra electrical power for functions disused in the future while maintaining the performance of communication between an electronic control unit and an external unit for development. The debug system includes an electronic control unit that has a microcomputer for controlling the operation of a control target, a transceiver circuit that is capable of communicating data with the microcomputer, and an external unit for development that is capable of rapidly communicating data with the transceiver circuit. The electronic control unit includes a power supply unit for supplying electrical power to the microcomputer. The transceiver circuit operates on electrical power supplied from an external power supply unit, which differs from the power supply unit included in the electronic control unit.

Description

[0001] Cross References to Related Applications [0002] The disclosure of Japanese Patent Application No. 2011-231538 filed on Oct. 21, 2011 including this specification, drawings and abstract is incorporated herein by reference in its entirety. technical field [0003] The invention relates to an information processing unit. The present invention also relates to a technique used by an information processing unit for establishing specific communication with an external unit, for example, relates to a technique effective for a microcomputer having a communication function. Background technique [0004] Many hardware products having electronic control units (ECUs) have been widely used due to advanced electronic control technology. For example, in most vehicles, ships, aircraft, and other moving bodies, electronic control units are used to control eg engines and navigation equipment. An information processing unit (for example, LSI) having a microcomputer is built in such a...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G05B23/02H04B1/40
CPCG06F1/26G06F1/3287G06F11/3648Y02D10/00G01R31/28G06F11/22G06F1/266G06F1/30G06F1/3212G06F1/3243
Inventor 椎名崇弘
Owner RENESAS ELECTRONICS CORP