Technological method capable of preventing shortcomings on photoresist during wet etching

Abstract

The invention provides a technological method capable of preventing shortcomings on photoresist during wet etching. The technological method comprises the steps that the photoresist is coated on a silicon slice where a shallow isolation groove is formed and a silicon oxide thin film is deposited; exposure and development of the photoresist are achieved, a first silicon oxide zone to be etched in a wetting mode and a second silicon oxide zone protected by the photoresist are exposed, the first silicon oxide zone and the second silicon oxide zone belongs to the silicon oxide thin film; in the same development machine table which carries out development, cross-linked material solution which contains amine compounds or polyamine compounds is coated on a photoresist pattern, heating is carried out, so that the amine compounds or the polyamine compounds react with the surface of the photoresist to form a macromolecule cross-linked protective film, and accordingly the photoresist pattern is solidified, then residual cross-linked material solution which contains the amine compounds or the polyamine compounds is removed; wet etching is carried out, so that the silicon oxide thin film on the first silicon oxide zone is removed partially; residual photoresist is removed, then the silicon oxide thin film is deposited again, and accordingly silicon oxide thin film double gate oxide with different thicknesses is formed in the first silicon oxide zone and the second silicon oxide zone.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, more specifically, the invention relates to a process method for preventing photoresist from producing defects during wet etching. Background technique [0002] Advanced integrated circuit chips usually integrate multiple functional devices. Devices with multiple functions generally need to correspond to different field effect transistors (FETs). The multiple gate oxide process is a common method for fabricating different field effect transistors in the same chip. There are several ways to implement multiple gate oxides. [0003] For example, Figure 1-Figure 5 Demonstrated the fabrication process flow of dual gate oxide. Coating photoresist 4 ( figure 1 ). After exposure and development, the region 5 to be wet-etched and the region 6 protected by the photoresist 4 are exposed ( figure 2 ). Wet etching thins or completely removes the silicon oxide film 3 in region 5 ( Figure ...

AI Technical Summary

Problems solved by technology

Failure to do so will result in distortion of the photoresist pattern and adversely affect production throughput

Due to the limitation of baking temperature and baking time, the compactness of the photoresist film after baking may not meet the requirements of acid solution corrosion resistance

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