A phase-locked loop and its clock generation method and circuit

Abstract

The present invention proposes a phase-locked loop for generating a clock signal. The phase-locked loop includes a digital control unit, the digital control unit generates a frequency division ratio adjustment signal; and an analog phase-locked loop unit, and the analog phase-locked loop unit adjusts the clock signal generated based on the frequency division ratio adjustment signal , characterized in that the analog phase-locked loop unit responds to the frequency division ratio adjustment signal to fine-tune the frequency of the generated clock signal, thereby realizing the tracking of the signal phase and the locking function of the input horizontal synchronization signal, so that the generated The frequency of the clock signal matches the required operating frequency. This kind of phase-locked loop avoids the limitation of low bandwidth when the full analog phase-locked loop is realized, the capacitance and resistance of the loop filter can be integrated into the chip to save cost, and also avoids the poor jitter performance of the full-digital phase-locked loop distortion rate high disadvantages.

Description

technical field [0001] The present invention relates to phase locked loops, and more particularly to methods and circuits for reducing clock jitter at the output of phase locked loops. Background technique [0002] In almost all high-speed electronic circuit systems, the phase-locked loop (PLL) has a very wide range of applications. The output clock performance of the phase-locked loop is very critical. The stability of the phase-locked loop and the performance of the output clock are directly related to the performance of the entire system. relevant. For example, in a high-resolution video analog front-end application, the system uses a phase-locked loop (analog or digital implementation) to synchronize the horizontal synchronization signal that needs to be displayed on the panel, and at the same time generates the pixel sampling clock required by the analog-to-digital converter . [0003] At present, due to the wide variety of video display formats, the resolutions of ea...

AI Technical Summary

Problems solved by technology

Generally speaking, this kind of phase switching circuit between multiple high-speed clocks is very prone to clock glitches, and the performance of its clock jitter is closely related to the physical implementation. The adjustment range and accuracy of the clock are also very limited, and it will introduce high switching noise

The whole system requires a large area, and the power consumption of the chip is also relatively large

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