Phase-locked loop and method and circuit for producing clock thereof

Abstract

The invention provides a phase-locked loop and a method and circuit for producing a clock of the phase-locked loop. The phase-locked loop comprises a digital control unit and an analog phase-locked loop unit, wherein the digital control unit produces frequency dividing ratio adjusting signals, and the analog phase-locked loop unit conducts adjustment on produced clock signals based on the frequency dividing ratio adjusting signals. The phase-locked loop is characterized in that the analog phase-locked loop unit conducts responding on the frequency dividing ratio adjusting signals to fine adjust the frequency of the produced clock signals, therefore, tracking for signal phases and a locking function for input horizontal-drive signals are achieved, and the frequency of the produced clock signals is made to conform to required work frequency. The phase-locked loop avoids limitation of a low bandwidth produced when a full analog phase-locked loop is achieved, capacitors and resistors of a loop filter can be integrated inside a chip to save cost, and the disadvantages that a full digital phase-locked loop is bad in shake performance and high in distortion rate are also avoided.

Description

technical field [0001] The present invention relates to phase locked loops, and more particularly to methods and circuits for reducing clock jitter at the output of phase locked loops. Background technique [0002] In almost all high-speed electronic circuit systems, the phase-locked loop (PLL) has a very wide range of applications. The output clock performance of the phase-locked loop is very critical. The stability of the phase-locked loop and the performance of the output clock are directly related to the performance of the entire system. relevant. For example, in high-resolution video analog front-end applications, the system uses a phase-locked loop (analog or digital implementation) to synchronize the horizontal synchronization signal that needs to be displayed on the panel, and at the same time generate the pixel sampling clock required by the analog-to-digital converter . [0003] At present, due to the wide variety of video display formats, the resolutions of each...

AI Technical Summary

Problems solved by technology

Generally speaking, this kind of phase switching circuit between multiple high-speed clocks is very prone to clock glitches, and the performance of its clock jitter is closely related to the physical implementation. The adjustment range and accuracy of the clock are also very limited, and it will introduce high switching noise

The whole system requires a large area, and the power consumption of the chip is also relatively large

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