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A network-on-chip data transmission device and method with hierarchical protection

A data transmission device and network-on-chip technology, which is applied in digital transmission systems, transmission systems, data exchange networks, etc., can solve problems affecting the transmission performance of the network-on-chip, high router cache overhead, and increased transmission power consumption, so as to reduce transmission delays and power consumption overhead, reduce latency and power consumption overhead, and reduce the effect of frequent operations

Inactive Publication Date: 2016-01-27
CENT SOUTH UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The usual methods are mainly divided into two categories: one is to rely on end-to-end (end-to-end) retransmission solutions, but when the error rate increases, the delay overhead caused by retransmission will greatly increase, seriously affecting the network on chip. transmission performance
The other is to implement strict hop-by-hop protection for all data, but this method will lead to a large router cache overhead and a sharp increase in transmission power consumption

Method used

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  • A network-on-chip data transmission device and method with hierarchical protection
  • A network-on-chip data transmission device and method with hierarchical protection
  • A network-on-chip data transmission device and method with hierarchical protection

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Embodiment Construction

[0037] Such as figure 1As shown, an embodiment of the present invention is described by taking a Mesh2x2 network topology structure as an example. The functions realized by the device are: headflit hop-to-hop (hop-by-hop) protection and data packet end-to-end (end-to-end) protection. The device includes a data encoding unit, a header protection unit and a data decoding unit. Among them, the data encoding unit and the data decoding unit are respectively located in the network interface of the sending end and the network interface of the receiving end, and are used to implement error-tolerant encoding and decoding of data packets, and perform end-to-end decoding when the number of errors exceeds the error-correcting capability of error-tolerant encoding. Retransmit the packet. Retransmitted packets are stored in the retransmission buffer of the sending network interface. The header protection unit is located in the router of the on-chip network, and is used to realize the pro...

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Abstract

The invention discloses an on-chip network data transmission device and method with a cascade protection function and belongs to the technical field of multi-core chips. The device comprises a data coding unit, a head protection unit and a data decoding unit, wherein the data coding unit is used for achieving fault-tolerant coding of all data of a data package; the head protection unit is used for achieving skip-to-skip protection for a head chip; the data decoding unit is used for achieving decoding of the data package, requesting end-to-end retransmission when the number of errors exceeds the error correcting capability of adopted codes, and thus achieving end-to-end protection for the data package. Meanwhile, the invention discloses the on-chip network data transmission method with the cascade protection function. Reliable protection is conducted at the two stages of the data package and the chip, namely, the end-to-end protection is conducted on the data package and the skip-to-skip protection is conducted on the head chip, and the method can be achieved through the device. The device and method not only ensure on-chip network reliability, but also achieve data transmission which is low in power consumption and short in delay time.

Description

technical field [0001] The invention relates to the technical field of multi-core chips, in particular to a hierarchically protected on-chip network data transmission device and method. Background technique [0002] Network-on-Chip (NoC) is widely considered to be the most promising communication infrastructure in large-scale multi-core chips. [0003] Due to the limitations of the on-chip network router cache, the packets transmitted in the on-chip network are divided into smaller units - flits (flit) for transmission. These slices are further divided into headflits and dataflits. The header contains the routing information of the data packet, that is, the routing of the entire data packet is determined by the header, and the data follows the header and moves to the target node. [0004] However, various software and hardware errors (such as single-event flip (soft error, crosstalk, etc.)) may cause the transmission failure of the network on chip. For example, an error i...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L1/00H04L1/18H04L12/70
Inventor 高建良王建新李欣
Owner CENT SOUTH UNIV
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