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Finfet method and structure with underlying embedded punch-through resistant layer

An anti-punch-through, through-layer technology, used in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., to solve problems such as damage to fins

Active Publication Date: 2016-04-06
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Injection through the fin can also damage the fin itself

Method used

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  • Finfet method and structure with underlying embedded punch-through resistant layer
  • Finfet method and structure with underlying embedded punch-through resistant layer
  • Finfet method and structure with underlying embedded punch-through resistant layer

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Embodiment Construction

[0030] Figure 1A A substrate 3 is shown. In some embodiments, substrate 3 is silicon, while in other embodiments, substrate 3 is formed of other suitable semiconductor materials. The substrate 3 is divided into an nFET part and a pFET part. exist Figure 1AIn the illustrated embodiment, a dotted line 5 separates the nFET portion from the pFET portion. Figure 1A The substrate 3 represents a multitude of nFET and pFET portions located on a semiconductor substrate and in various spatial arrangements relative to each other. The nFET and pFET sections do not overlap. An n-type anti-punchthrough (APT) layer 7 is provided in the nFET portion of the substrate 3 , while a p-type APT layer 9 is provided in the pFET portion of the substrate 3 . In various embodiments, n-type APT layer 7 and p-type APT layer 9 are formed in or on the upper surface of substrate 3 . In one embodiment, n-type APT layer 7 and p-type APT layer 9 are formed by ion implantation, while in another embodime...

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Abstract

Methods and structures are provided for forming semiconductor FinFET devices with superior repeatability and reliability, the methods and structures including providing an APT (Anti-Punch Through) layer precisely formed under the semiconductor fins. The n-type APT layer and the p-type APT layer are formed before the semiconductor fin-forming material is formed. In some embodiments, a barrier layer is added between the precisely positioned APT layer and the semiconductor fins. An appropriately doped APT layer is formed in the surface of the semiconductor substrate by ion implantation and epitaxial growth. Fin material is formed over the APT layer using epitaxial growth / deposition methods. The present invention provides a FinFET method and structure with an underlying embedded punchthrough resistant layer.

Description

technical field [0001] Generally, the present invention relates to semiconductor devices and methods for fabricating semiconductor devices. More specifically, the present invention relates to methods and structures for FinFET structures with an underlying embedded punchthrough anti-layer. Background technique [0002] With increasing concerns about cost and reliability, there is a continuing demand for semiconductor devices with higher integration (ie, higher packing density of transistors and other devices). To improve integration, FinFET (Fin Field Effect Transistor) devices are becoming more common in semiconductor integrated circuits and other semiconductor devices in various applications. A FinFET device is a transistor that utilizes a semiconductor fin extending above the surface of a substrate as the channel region of the transistor. Such a channel region has an increased area relative to a transistor with a planar channel. However, in many cases, efforts to reduce...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L29/78
CPCH01L21/823821
Inventor 吴伟豪杨凯杰谢文兴后藤贤一吴志强
Owner TAIWAN SEMICON MFG CO LTD