A method for automatic layout of tsv positions in 3D integrated circuits based on noise reduction

Abstract

The invention relates to a noise-reduction-based automatic layout method for the positions of TSVs in a 3D integrated circuit. An input unit, a moving unit, an adjusting unit, a storage unit, a judging unit and a bouncing-off unit are adopted in the method, wherein the input unit is used for establishing a rectangular coordinate system of the 3D integrated circuit and initially determining the coordinates where the TSVs are located, the moving unit is used for moving signal TSVs to integer coordinate points, the adjusting unit is used for adjusting the positions of surplus TSVs, the storage unit is used for finding TSV pairs with the intervals equal to the scale standard through a circle drawing method, the judging unit is used for judging whether optimizing needs to be conducted, and the bouncing-off unit is used for bouncing off the TSV pairs with the intervals equal to the scale standard. According to the noise-reduction-based automatic layout method for the positions of the TSVs in the 3D integrated circuit, an original circuit structure is not damaged, simple relayout is conducted on the TSV layout on which initial layout is conducted, the positions of the TSVs in the 3D integrated circuit layout are standardized, the length of an interconnecting line is reduced, the intervals of the TSVs are reasonably increased, the aim of capacitive noise reduction is achieved, and automatic layout of the TSVs is optimized.

Description

technical field [0001] The invention relates to an automatic layout method for TSV positions in a 3D integrated circuit, which belongs to the field of circuit design, and in particular to an automatic layout method for TSV positions in a 3D integrated circuit based on the purpose of noise reduction. Background technique [0002] With the rapid development of integrated circuit design and manufacturing, a single chip can integrate hundreds of millions of transistors. However, with the continuous improvement of integration, the number of device units on each chip increases sharply, the chip area increases, and the growth of inter-unit connections not only affects the working speed of the circuit but also takes up a lot of area, which seriously affects the further improvement of the integrated level and working speed of the integrated circuit. . In this case, three-dimensional chip integration technology has become a new development idea. In addition, brand-new device structu...

AI Technical Summary

Problems solved by technology

Another driver of 3D integration is the issue of memory speed lag, as memory access speeds are known to evolve slowly relative to processor speed, causing the processor to be stalled while it waits for the memory to fetch data

At present, the continuous reduction of chip power supply voltage affects the noise resistance of digital circuits, and the addition of more high-performance modules makes it more and more difficult to analyze the noise of the circuit

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