A method for automatic layout of power/groundtsv positions in 3D integrated circuits
An integrated circuit and automatic layout technology, applied in electrical digital data processing, special data processing applications, instruments, etc., can solve problems such as electric field coupling noise, interference circuit, signal interference noise, etc., to reduce capacitive noise and reduce electric field. the effect of strength
Active Publication Date: 2016-08-17
BEIJING UNIV OF TECH
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Problems solved by technology
This is because when the signal is propagating, a part of the electric field of the signal path and the return path extends to the surrounding adjacent space to form a fringe field. Continued wiring in this fringe field area will generate coupling noise of the electric field, which interferes with the circuit.
The coupling capacitance generated between the two TSVs will cause unnecessary interference noise to the signal, thus affecting the effective work of the 3D integrated circuit
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[0031] The present invention will be further described below in conjunction with accompanying drawing.
[0032] Such as figure 1Shown is a schematic cross-sectional structure diagram of a 3D integrated circuit chip, the 3D integrated circuit chip includes signal TSV1, powerTSV2, groundTSV3, top chip 6, bottom chip 7, standard unit 8, metal interconnection 9 and substrate 10; the present invention includes five units, respectively input unit, linear layout unit, shielding unit, grid distribution unit, power supply layout unit; 3D integrated circuit in the present invention is a kind of three-dimensional chip structure, and each layer of 3D integrated circuit is 2D chip, and is connected vertically by TSV; the top-level chip 6 and the low-level chip 7 constitute the general structure of the chip; the standard unit 8 in the chip is the basic component for realizing signal interconnection in the integrated circuit, and the metal interconnection line 9 Complete the interconnection...
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The invention relates to an automatic layout method for power / ground TSV positions in a 3D integrated circuit. An input unit is used for establishing a rectangular coordinate system of the 3D integrated circuit and initially determining coordinates of TSVs. A linear layout unit is used for horizontally moving signal TSVs to the closest straight lines. A shield unit is used for inserting ground TSVs and reducing noise between the signal TSVs. A grid distribution unit is used for establishing a secondary grid in a TSV layout chart. A power supply layout unit is used for inserting power TSVs to supply power to chips. According to the TSV layout chart with the given initial layout, capacitive noise may be produced between every two TSVs. Through the method of inserting the power TSVs and the ground TSVs, the electric field intensity between the TSVs can be effectively reduced, so that the purpose of shielding is achieved. Consequently, the capacitive noise caused by capacity coupling between the TSVs is reduced, and power can be supplied to the chips ceaselessly.
Description
technical field [0001] The invention relates to an automatic layout method for a 3D integrated circuit, belonging to the field of circuit design, in particular to an automatic layout method for power / groundTSV positions in a 3D integrated circuit. Background technique [0002] In recent years, with the rapid development of integrated circuit technology and the increasingly broad development prospects, the packaging of integrated circuits has gradually developed towards miniaturization, high speed, high power, multi-pin, high density, and high reliability. Today, traditional integrated circuits It is increasingly difficult to meet this demand in two-dimensional planar assembly. In order to solve the market and technical needs, people began to study the use of micro-assembly technology to develop from two-dimensional planar assembly technology to three-dimensional three-dimensional assembly technology. Therefore, three-dimensional (3D) packaging breaks through the traditional...
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IPC IPC(8): G06F17/50
Inventor 侯立刚梁翔汪金辉路博彭晓宏耿淑琴
Owner BEIJING UNIV OF TECH