Clock locking method and device for multi-phase clock generation system

Abstract

The invention provides a clock locking method and device of a multi-phase clock generating system. The system comprises a digital delaying chain formed by N DCDLs. Each DCDL comprises a first DC chain and a second DC chain. Each first DC chain comprises at least one first DC. The method comprises the steps that delaying of each first DC chain is adjusted according to adjusting codes, and when a clock phase output by the digital delaying chain lags behind a reference clock phase, first-time locking is carried out; the last single bit of the adjusting codes during locking is reset, so that delaying of the digital delaying chain backspaces by delaying of the N first DCs, and then first clock signals are output; according to the first clock signals and the reference clock signals, remainder codes are generated; and according to the remainder codes, the phase difference between the first clock signals and the reference clock signals is evenly compensated into the digital delaying chain with delaying of the second DCs as units, and accordingly the delaying errors between the phase of the first clock signals output by the multi-phase clock generating system and the phase of a reference clock are reduced.

Description

technical field [0001] The invention relates to the field of communication technology, in particular to a clock locking method and device for a multi-phase clock generation system. Background technique [0002] With the continuous improvement of the main frequency of VLSI and the continuous increase of parallel data requests between chips, the system puts forward higher requirements on the bandwidth of the communication system between chips. In a high-speed, parallel inter-chip communication system, it is necessary to perform serial-to-parallel conversion and synchronization on the data transmitted by multiple parallel channels, which puts forward an urgent demand for a multi-phase clock generation system. Taking the communication between two chips as an example (chip A and chip B respectively, chip A is the sending end, and chip B is the receiving end), the data is transmitted in parallel in the inside of chip A and chip B; when chip A When the multi-channel parallel data ...

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Problems solved by technology

[0004] However, in the multi-phase clock generation system of the prior art, the ideal output in each DCDL is an 8-phase clock of 45° to 360°, and the phase interval of each phase clock is 45°, but since the DC in each DCDL is actually used There is an error between the actual delay length and the ideal delay length of the DC-built components. The lock-in adjustment step is too large, and the error will increase proportionally with the increase in the number of phases of the output clock. Compared with the standard ideal, the delay of DCDL is very small. Under the cumulative effect of multi-phase clocks, there will be a large delay deviation between the sampling phase of the subsequent clock and the standard ideal phase, resulting in an increase in error.

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