Segmented and parallel compression method and system for nonvolatile processor

Abstract

The invention discloses a segmented and parallel compression method and a segmented and parallel compression system for a nonvolatile processor, and relates to the field of low-power-consumption processors. The method comprises the following steps: 1) determining the number of divided segments of a status bit of a segmented volatile memory unit of the nonvolatile processor; 2) compiling an offline / online hybrid algorithm, and performing compression simulation to each status bit segment by using an offline segment algorithm to obtain division of all segments with equal average compression time, average compression time and compression time standard difference of each segment; 3) designing the nonvolatile processor according to the number of the segments of the status bit and the length of each segment obtained through the offline segment algorithm; 4) connecting each status bit segment with a corresponding compression module in a parallel compression unit and performing dynamic load balancing to each status bit segment with greater compression time standard difference by using an online control algorithm to complete compression backup. The system comprises a volatile processing logic unit, the segmented volatile memory unit, the parallel compression unit and a segmented nonvolatile memory unit.

Description

technical field [0001] The invention relates to the field of low-power processor design, in particular to a segmented parallel compression method and system applied to non-volatile processors. Background technique [0002] In recent years, with the development of microprocessors and low power consumption, nonvolatile processors (Nonvolatile Processor) have received more and more attention. The non-volatile processor is a new type of processor that replaces all registers and above-level storage units in traditional processors with non-volatile storage units. It has traditional processors such as zero standby, high-speed sleep and wake-up, and continuous operation under intermittent power supply conditions. It has the incomparable advantages of traditional processors in the low-power embedded field. [0003] The common non-volatile processor adopts the full replacement technology. The implementation method is to replace all the system registers with non-volatile registers, wh...

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Problems solved by technology

[0003] The common non-volatile processor adopts the full replacement technology. The implementation method is to replace all the system registers with non-volatile registers, which can perform register-level parallel backup, but this technology will greatly increase the chip area.

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