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A system and method for realizing direct memory access

A technology for implementing a system and an implementation method, applied in the field of network communication, can solve the problems of idle working cycle of memory, insufficient memory performance, and reduced efficiency of processing system events, and achieve the effect of flexible processing

Active Publication Date: 2017-08-04
PHICOMM (SHANGHAI) CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a system and method for implementing direct memory access, which is used to solve the problem that the memory performance cannot be fully utilized in the DMA mode memory stage inside the CPU in the prior art. A considerable part of the memory working cycle is idle, and the CPU will give up the operation of the memory on the system bus when executing the DMA mode. At this time, if the CPU prohibits certain memory operations, the CPU is in a suspended state, which reduces the The CPU's efficiency in processing system events is greatly reduced

Method used

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  • A system and method for realizing direct memory access
  • A system and method for realizing direct memory access
  • A system and method for realizing direct memory access

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Experimental program
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Embodiment 1

[0050] This embodiment provides a direct memory access implementation system 1, the system 1 is applied to a rack-mounted device 3 connected to a source module 2 that generates operation, management and maintenance messages and data, and the rack The conventional equipment includes a central processing module 31 for processing the operation, management and maintenance messages and data, please refer to figure 1 , is shown as a schematic structure diagram of a direct memory access implementation system. The direct memory access implementation system 1 includes: a switching module 11 , a switching module 12 , a data packet control module 13 and a plurality of random storage modules 14 . In this embodiment, the random storage module 14 may use DDR2 or DDR3 or the like.

[0051] The switch module 11 is connected to the source module 2 for when the source module 2 sends a DMA (direct memory access) request and transmits the operation, management and maintenance messages and data ge...

Embodiment 2

[0058] This embodiment provides a method for implementing direct memory access, which is applied to a system for implementing direct memory access in rack-mounted equipment for big data exchange connected to source modules that generate operation, management, maintenance messages and data. The rack-mounted equipment includes a central processing module for processing the operation, management and maintenance messages and data, the realization system of the direct memory access includes a switching module connected to the source module, and a switching module connected to the switching module module, the switching module is also connected with the central processing module and the data message control module, and hangs on a plurality of random storage modules of the data message control module, please refer to Figure 5 , which is shown as a flowchart of an implementation method of direct memory access, and the implementation method of direct memory access includes:

[0059] S1...

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Abstract

The invention provides a direct memory access achievement system. The system comprises a switching module, a switchover module, a data and message control module and a center processing module, wherein the switching module is used for transmitting generated messages and data when a source module sends out a DMA request; the switchover module is used for directly sending the DMA request, the messages and the data when the DMA request sent by the source module, the messages and the data are received; the data and message control module is used for responding to the DMA request and judging whether the messages and the data are in an emergent state according to prestored data and message priorities, if the answer is positive, the center processing module processes the messages and the data, and if the answer is negative, the messages and the data are written into a random storage module under the data and message control module for caching, when the data and message control module detects the center processing module and processes the messages and the data in the emergent state, the messages and the data cached in the random storage module are read, and the center processing module processes the messages and the data. A DDR under an FPGA and a CPU share the memory, handling capacity of the system for the big data and the messages is greatly improved, and efficiency of the CPU processing system events is improved.

Description

technical field [0001] The invention belongs to the technical field of network communication, and in particular relates to a system and method for realizing direct memory access. Background technique [0002] In the rack-mounted equipment for big data exchange, a large number of OAM (operation, administration, maintenance) messages and data need to be reported to the CPU every moment during the exchange, which needs to be communicated with the CPU Achieve sharing. But the CPU itself also carries a large number of other system management tasks. [0003] In a traditional design, these messages and data information are usually exchanged by using the PCIe bus in the exchange to communicate with the bus of the CPU. Doing so itself will occupy a large number of running time slots of the CPU to ensure that these data and messages are processed accordingly, which actually reduces the system efficiency of the system itself. In the process of processing a large amount of data by th...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/16
Inventor 李军
Owner PHICOMM (SHANGHAI) CO LTD