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A method for sorting received packets and processing invalid packets

A packet processing and receiving packet technology, applied in the field of network communication, can solve problems such as poor recovery accuracy, loss of clock information, long recovery time, etc.

Active Publication Date: 2017-05-03
CHENGDU LONGRAISE TECH DEV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] like figure 1 As shown, CES (Circuit Emulation Service) circuit emulation provides a smooth transition solution from the circuit switching network to the packet switching network. The PE device at the sending end encapsulates the TDM data in real time, and transmits it to the receiving end through the packet network. The data buffer queue at the receiving end of the device recovers the synchronous clock, the synchronous clock decapsulates the data frame, and reassembles it into a TDM data stream; but because the TDM network is a synchronous network, and the packet network is a typical asynchronous network, TDM data is transmitted to At the receiving end, it will cause its own clock information to be lost. Therefore, the clock recovery technology is very important when recovering TDM data at the receiving end. The recovery of data clock information directly affects the quality of data transmission. The current clock recovery technology has the time required for recovery. Long, poor recovery accuracy and other issues

Method used

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  • A method for sorting received packets and processing invalid packets
  • A method for sorting received packets and processing invalid packets
  • A method for sorting received packets and processing invalid packets

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0083] Embodiment 1: as figure 2 As shown, this embodiment provides a TDM-based network clock recovery system with high recovery accuracy and short recovery time; it includes a data clock branching module 1, a received packet sorting and invalid packet processing system 2, a clock recovery module 3, Parallel-serial processing module 4; said data clock branching module 1 is respectively connected with said receiving packet sorting and invalid packet processing system 2, clock recovery module 3; said receiving packet sorting and invalid packet processing system 2, said clock recovery The modules 3 are all connected to the parallel-serial processing module 4 .

[0084] The data clock branching module 1 is used to send the control word part of the network data received from the packet network to the clock recovery module 3 .

[0085] The received packet sorting and invalid packet processing system 2 is used to sort the network data and process packet loss.

[0086] The clock re...

Embodiment 2

[0104] Embodiment 2: This embodiment also provides a TDM-based network clock recovery method with high recovery accuracy and short recovery time, such as Figure 5 As shown, the following steps are included: Step S100 is included: encapsulating the network data to be transmitted according to the specified number of frames.

[0105] Including step S200: separating the control word part from the received network data, and calculating and adjusting the recovered clock.

[0106] Step S300 is included: sorting and discarding received network data.

[0107] Step S400 is included: performing parallel-serial processing on the sorted and packet loss-processed network data and the calculated and adjusted recovered clock frequency, so as to realize the clock recovery of the network data.

[0108] Further, such as Figure 6 As shown, in the step S200 of extracting the timing sequence number from the control word part and counting according to the current recovered clock: including step ...

Embodiment 3

[0163]Embodiment 3: This embodiment also provides a TDM-based network clock recovery method with high recovery accuracy and short recovery time, such as Figure 5 As shown, the following steps are included: Step S100 is included: encapsulating the network data to be transmitted according to the specified number of frames.

[0164] Including step S200: separating the control word part from the received network data, and calculating and adjusting the recovered clock.

[0165] Step S300 is included: sorting and discarding received network data.

[0166] Step S400 is included: performing parallel-serial processing on the sorted and packet loss-processed network data and the calculated and adjusted recovered clock frequency, so as to realize the clock recovery of the network data.

[0167] Further, such as Figure 6 As shown, in the step S200 of extracting the timing sequence number from the control word part and counting according to the current recovered clock: including step S...

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PUM

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Abstract

The invention relates to the field of network communication, particularly to a received packet sorting and invalid packet processing method. The method comprises a storing method for direct storage into corresponding positions according to serial numbers of network data as well as a reading method for one-time reading of caching data according to a read pointer, meanwhile, flag bit writing and reading methods are set according to storage and reading of every packet, numbers of valid packets, repetitive packets, lost packets and invalid packets which are received by a system are counted, and the performance of the system is evaluated in real time.

Description

technical field [0001] The invention relates to the field of network communication, in particular to a method for sorting received packets and processing invalid packets. Background technique [0002] Such as figure 1 As shown, CES (Circuit Emulation Service) circuit emulation provides a smooth transition solution from the circuit switching network to the packet switching network. The PE device at the sending end encapsulates the TDM data in real time, and transmits the TDM data to the receiving end through the packet network. At the receiving end, the PE The data buffer queue at the receiving end of the device recovers the synchronous clock, and the synchronous clock decapsulates the data frame and reassembles it into a TDM data stream; however, because the TDM network is a synchronous network, and the packet network is a typical asynchronous network, TDM data is transmitted through the packet network to At the receiving end, it will cause its own clock information to be l...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L1/00
CPCH04L1/0036
Inventor 胡强吴援明刘思卓
Owner CHENGDU LONGRAISE TECH DEV